Trait Instruction 

pub trait Instruction:
    Display
    + Debug
    + Copy
    + Send
    + Sync
    + Sized {
    type Reg: Register;

    // Required methods
    fn try_decode(instruction: u32) -> Option<Self>;
    fn alignment() -> u8;
    fn size(&self) -> u8;
}

Generic instruction

Required Associated Types

type Reg: Register

A register type used by the instruction

Required Methods

fn try_decode(instruction: u32) -> Option<Self>

Try to decode a single valid instruction

fn alignment() -> u8

Instruction alignment in bytes

fn size(&self) -> u8

Instruction size in bytes

Dyn Compatibility

This trait is not dyn compatible.

In older versions of Rust, dyn compatibility was called "object safety".

Implementors

impl<Reg> Instruction for Rv32BInstruction<Reg>

where Reg: Register<Type = u32>,

type Reg = Reg

impl<Reg> Instruction for Rv32Instruction<Reg>

where Reg: Register<Type = u32>,

type Reg = Reg

impl<Reg> Instruction for Rv32MInstruction<Reg>

where Reg: Register<Type = u32>,

type Reg = Reg

impl<Reg> Instruction for Rv32ZbaInstruction<Reg>

where Reg: Register<Type = u32>,

type Reg = Reg

impl<Reg> Instruction for Rv32ZbbInstruction<Reg>

where Reg: Register<Type = u32>,

type Reg = Reg

impl<Reg> Instruction for Rv32ZbcInstruction<Reg>

where Reg: Register<Type = u32>,

type Reg = Reg

impl<Reg> Instruction for Rv32ZbkbInstruction<Reg>

where Reg: Register<Type = u32>,

type Reg = Reg

impl<Reg> Instruction for Rv32ZbkcInstruction<Reg>

where Reg: Register<Type = u32>,

type Reg = Reg

impl<Reg> Instruction for Rv32ZbkxInstruction<Reg>

where Reg: Register<Type = u32>,

type Reg = Reg

impl<Reg> Instruction for Rv32ZbsInstruction<Reg>

where Reg: Register<Type = u32>,

type Reg = Reg

impl<Reg> Instruction for Rv32ZcaInstruction<Reg>

where Reg: Register<Type = u32>,

type Reg = Reg

impl<Reg> Instruction for Rv32ZcbInstruction<Reg>

where Reg: Register<Type = u32>,

type Reg = Reg

impl<Reg> Instruction for Rv32ZcmpInstruction<Reg>

where Reg: Register<Type = u32> + ZcmpRegister<Type = u32>,

type Reg = Reg

impl<Reg> Instruction for Rv32ZknInstruction<Reg>

where Reg: Register<Type = u32>,

type Reg = Reg

impl<Reg> Instruction for Rv32ZkndInstruction<Reg>

where Reg: Register<Type = u32>,

Encoding layout (R-type, opcode 0x33, funct3 0x0):

[31:30] bs       - 2-bit byte select
[29:25] funct5   - 0b1_0101 (aes32dsi) / 0b1_0111 (aes32dsmi)
[24:20] rs2
[19:15] rs1
[14:12] funct3   - 0b000
[11:7]  rd
[6:0]   opcode   - 0b011_0011 (OP)

Ratified match/mask values (from riscv-opcodes): MATCH_AES32DSI = 0x2a00_0033, MASK_AES32DSI = 0x3e00_707f MATCH_AES32DSMI = 0x2e00_0033, MASK_AES32DSMI = 0x3e00_707f

rd and rs1 are independent fields. The assembler convention places the accumulator in both rd and rs1 (the rt pattern), but the hardware does not require rd == rs1 and the decoder must not enforce it.

type Reg = Reg

impl<Reg> Instruction for Rv32ZkneInstruction<Reg>

where Reg: Register<Type = u32>,

Encoding layout (R-type, opcode 0x33, funct3 0x0):

[31:30] bs       - 2-bit byte select
[29:25] funct5   - 0b1_0001 (aes32esi) / 0b1_0011 (aes32esmi)
[24:20] rs2
[19:15] rs1
[14:12] funct3   - 0b000
[11:7]  rd
[6:0]   opcode   - 0b011_0011 (OP)

Ratified match/mask values (from riscv-opcodes): MATCH_AES32ESI = 0x2200_0033, MASK_AES32ESI = 0x3e00_707f MATCH_AES32ESMI = 0x2600_0033, MASK_AES32ESMI = 0x3e00_707f

rd and rs1 are independent fields. The assembler convention places the accumulator in both rd and rs1 (the rt pattern), but the hardware does not require rd == rs1 and the decoder must not enforce it.

type Reg = Reg

impl<Reg> Instruction for Rv32ZknhInstruction<Reg>

where Reg: Register<Type = u32>,

type Reg = Reg

impl<Reg> Instruction for Rv32ZmmulInstruction<Reg>

where Reg: Register<Type = u32>,

type Reg = Reg

impl<Reg> Instruction for Rv64BInstruction<Reg>

where Reg: Register<Type = u64>,

type Reg = Reg

impl<Reg> Instruction for Rv64Instruction<Reg>

where Reg: Register<Type = u64>,

type Reg = Reg

impl<Reg> Instruction for Rv64MInstruction<Reg>

where Reg: Register<Type = u64>,

type Reg = Reg

impl<Reg> Instruction for Rv64ZbaInstruction<Reg>

where Reg: Register<Type = u64>,

type Reg = Reg

impl<Reg> Instruction for Rv64ZbbInstruction<Reg>

where Reg: Register<Type = u64>,

type Reg = Reg

impl<Reg> Instruction for Rv64ZbcInstruction<Reg>

where Reg: Register<Type = u64>,

type Reg = Reg

impl<Reg> Instruction for Rv64ZbkbInstruction<Reg>

where Reg: Register<Type = u64>,

type Reg = Reg

impl<Reg> Instruction for Rv64ZbkcInstruction<Reg>

where Reg: Register<Type = u64>,

type Reg = Reg

impl<Reg> Instruction for Rv64ZbkxInstruction<Reg>

where Reg: Register<Type = u64>,

type Reg = Reg

impl<Reg> Instruction for Rv64ZbsInstruction<Reg>

where Reg: Register<Type = u64>,

type Reg = Reg

impl<Reg> Instruction for Rv64ZcaInstruction<Reg>

where Reg: Register<Type = u64>,

type Reg = Reg

impl<Reg> Instruction for Rv64ZcbInstruction<Reg>

where Reg: Register<Type = u64>,

type Reg = Reg

impl<Reg> Instruction for Rv64ZcmpInstruction<Reg>

where Reg: Register<Type = u64> + ZcmpRegister<Type = u64>,

type Reg = Reg

impl<Reg> Instruction for Rv64ZknInstruction<Reg>

where Reg: Register<Type = u64>,

type Reg = Reg

impl<Reg> Instruction for Rv64ZkndInstruction<Reg>

where Reg: Register<Type = u64>,

type Reg = Reg

impl<Reg> Instruction for Rv64ZkneInstruction<Reg>

where Reg: Register<Type = u64>,

type Reg = Reg

impl<Reg> Instruction for Rv64ZknhInstruction<Reg>

where Reg: Register<Type = u64>,

type Reg = Reg

impl<Reg> Instruction for Rv64ZmmulInstruction<Reg>

where Reg: Register<Type = u64>,

type Reg = Reg

impl<Reg> Instruction for ZicondInstruction<Reg>

where Reg: Register,

type Reg = Reg

impl<Reg> Instruction for ZicsrInstruction<Reg>

where Reg: Register,

type Reg = Reg

impl<Reg> Instruction for ZvbbInstruction<Reg>

where Reg: Register,

type Reg = Reg

impl<Reg> Instruction for ZvbcInstruction<Reg>

where Reg: Register,

type Reg = Reg

impl<Reg> Instruction for ZveXxInstruction<Reg>

where Reg: Register,

type Reg = Reg

impl<Reg> Instruction for ZvkbInstruction<Reg>

where Reg: Register,

type Reg = Reg