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Instruction

Trait Instruction 

Source
pub trait Instruction:
    Display
    + Debug
    + Copy
    + Send
    + Sync
    + Sized
    + 'static {
    type Hart: HartConfig;

    const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension];
    const OWN_ISA_EXTENSIONS: &'static [IsaExtension];
    const ALIGNMENT: u8;
    const ISA_STRING: &'static str = _;

    // Required methods
    fn try_decode(instruction: u32) -> Option<Self>;
    fn size(&self) -> u8;

    // Provided method
    fn implements_extension<E>() -> bool
       where E: Instruction<Hart = Self::Hart> { ... }
}
Expand description

Generic instruction

Required Associated Constants§

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const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]

All implemented extensions, including this instruction itself, with their ISA extensions.

An inherited extension is implemented when at least one of its own instructions is present in the instruction set (otherwise it was ignored in one way or another) and the same is true for all extensions it inherits. Extensions without own instructions (like B) are implemented when all extensions they inherit are. So individual instructions ignored by name (like ecall in an instruction set without system calls) or missing due to their conditions (like amocas.b from Zabha without Zacas) don’t exclude the extension.

Note that this constant is auto-generated by the macro and usually doesn’t need to be specified explicitly (and if done, will cause conflicts at compile time).

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const OWN_ISA_EXTENSIONS: &'static [IsaExtension]

ISA extensions defined by this instruction enum itself, without inherited ones.

Empty for instruction enums that are not extensions on their own, like a collection of instructions shared by multiple extensions. Can also contain extensions implied by this instruction enum that are not modeled as instruction enums, like zvl*b for vector extensions.

Unsupported hart configuration results in a compilation error when this constant is used.

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const ALIGNMENT: u8

Instruction alignment in bytes, also known as IALIGN

Provided Associated Constants§

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const ISA_STRING: &'static str = _

ISA string as used in the Tag_RISCV_arch attribute of ELF files, for example, rv64i2p1_m2p0_zmmul1p0.

Contains ISA extensions of all implemented extensions (see Self::IMPLEMENTED_EXTENSIONS) in canonical order without duplicates. Only an instruction set with a base ISA (i or e) has the rv32/rv64 prefix, for others it only lists extensions, like m2p0_zmmul1p0.

Note that this constant is not supposed to be specified explicitly.

Required Associated Types§

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type Hart: HartConfig

Hart configuration of the implementation

Required Methods§

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fn try_decode(instruction: u32) -> Option<Self>

Try to decode a single valid instruction

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fn size(&self) -> u8

Instruction size in bytes

Provided Methods§

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fn implements_extension<E>() -> bool
where E: Instruction<Hart = Self::Hart>,

Checks whether this instruction implements the given extension, see Self::IMPLEMENTED_EXTENSIONS for details

Dyn Compatibility§

This trait is not dyn compatible.

In older versions of Rust, dyn compatibility was called "object safety".

Implementors§

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impl<Reg, Hart> Instruction for Rv32AInstruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv32BInstruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv32Instruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv32MInstruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv32ZaamoInstruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv32ZabhaInstruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv32ZacasInstruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv32ZalasrInstruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv32ZalrscInstruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv32ZbaInstruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv32ZbbInstruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv32ZbbZbkbSharedInstruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv32ZbcInstruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv32ZbkbInstruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv32ZbkcInstruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv32ZbkxInstruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv32ZbsInstruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv32ZcaInstruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv32ZcbInstruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv32ZcmpInstruction<Hart>
where Reg: Register<Type = u32> + ZcmpRegister<Type = u32>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv32ZknInstruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv32ZkndInstruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

Encoding layout (R-type, opcode 0x33, funct3 0x0):

[31:30] bs       - 2-bit byte select
[29:25] funct5   - 0b1_0101 (aes32dsi) / 0b1_0111 (aes32dsmi)
[24:20] rs2
[19:15] rs1
[14:12] funct3   - 0b000
[11:7]  rd
[6:0]   opcode   - 0b011_0011 (OP)

Ratified match/mask values (from riscv-opcodes): MATCH_AES32DSI = 0x2a00_0033, MASK_AES32DSI = 0x3e00_707f MATCH_AES32DSMI = 0x2e00_0033, MASK_AES32DSMI = 0x3e00_707f

rd and rs1 are independent fields. The assembler convention places the accumulator in both rd and rs1 (the rt pattern), but the hardware does not require rd == rs1 and the decoder must not enforce it.

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impl<Reg, Hart> Instruction for Rv32ZkneInstruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

Encoding layout (R-type, opcode 0x33, funct3 0x0):

[31:30] bs       - 2-bit byte select
[29:25] funct5   - 0b1_0001 (aes32esi) / 0b1_0011 (aes32esmi)
[24:20] rs2
[19:15] rs1
[14:12] funct3   - 0b000
[11:7]  rd
[6:0]   opcode   - 0b011_0011 (OP)

Ratified match/mask values (from riscv-opcodes): MATCH_AES32ESI = 0x2200_0033, MASK_AES32ESI = 0x3e00_707f MATCH_AES32ESMI = 0x2600_0033, MASK_AES32ESMI = 0x3e00_707f

rd and rs1 are independent fields. The assembler convention places the accumulator in both rd and rs1 (the rt pattern), but the hardware does not require rd == rs1 and the decoder must not enforce it.

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impl<Reg, Hart> Instruction for Rv32ZknhInstruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv32ZmmulInstruction<Hart>
where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64AInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64BInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64Instruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64MInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64ZaamoInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64ZabhaInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64ZacasInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64ZalasrInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64ZalrscInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64ZbaInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64ZbbInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64ZbbZbkbSharedInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64ZbcInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64ZbkbInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64ZbkcInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64ZbkxInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64ZbsInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64ZcaInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64ZcbInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64ZcmpInstruction<Hart>
where Reg: Register<Type = u64> + ZcmpRegister<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64ZknInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64ZkndInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64ZkndZkneSharedInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64ZkneInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64ZknhInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for Rv64ZmmulInstruction<Hart>
where Reg: Register<Type = u64>, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for ZawrsInstruction<Hart>
where Reg: Register, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for ZicondInstruction<Hart>
where Reg: Register, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for ZicsrInstruction<Hart>
where Reg: Register, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for ZifenceiInstruction<Hart>
where Reg: Register, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for ZkrInstruction<Hart>
where Reg: Register, Hart: HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for ZvbbInstruction<Hart>
where Reg: Register, Hart: VectorHartConfig<Reg = Reg> + HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for ZvbcInstruction<Hart>
where Reg: Register, Hart: VectorHartConfig<Reg = Reg> + HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for ZveXxInstruction<Hart>
where Reg: Register, Hart: VectorHartConfig<Reg = Reg> + HartConfig<Reg = Reg>,

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impl<Reg, Hart> Instruction for ZvkbInstruction<Hart>
where Reg: Register, Hart: VectorHartConfig<Reg = Reg> + HartConfig<Reg = Reg>,