pub trait Instruction:
Display
+ Debug
+ Copy
+ Send
+ Sync
+ Sized
+ 'static {
type Hart: HartConfig;
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension];
const OWN_ISA_EXTENSIONS: &'static [IsaExtension];
const ALIGNMENT: u8;
const ISA_STRING: &'static str = _;
// Required methods
fn try_decode(instruction: u32) -> Option<Self>;
fn size(&self) -> u8;
// Provided method
fn implements_extension<E>() -> bool
where E: Instruction<Hart = Self::Hart> { ... }
}Expand description
Generic instruction
Required Associated Constants§
Sourceconst IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
All implemented extensions, including this instruction itself, with their ISA extensions.
An inherited extension is implemented when at least one of its own instructions is present
in the instruction set (otherwise it was ignored in one way or another) and the same is true
for all extensions it inherits. Extensions without own instructions (like B) are
implemented when all extensions they inherit are. So individual instructions ignored by name
(like ecall in an instruction set without system calls) or missing due to their conditions
(like amocas.b from Zabha without Zacas) don’t exclude the extension.
Note that this constant is auto-generated by the macro and usually doesn’t need to be specified explicitly (and if done, will cause conflicts at compile time).
Sourceconst OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
ISA extensions defined by this instruction enum itself, without inherited ones.
Empty for instruction enums that are not extensions on their own, like a collection of
instructions shared by multiple extensions. Can also contain extensions implied by this
instruction enum that are not modeled as instruction enums, like zvl*b for vector
extensions.
Unsupported hart configuration results in a compilation error when this constant is used.
Provided Associated Constants§
Sourceconst ISA_STRING: &'static str = _
const ISA_STRING: &'static str = _
ISA string as used in the Tag_RISCV_arch attribute of ELF files, for example,
rv64i2p1_m2p0_zmmul1p0.
Contains ISA extensions of all implemented extensions (see Self::IMPLEMENTED_EXTENSIONS)
in canonical order without duplicates. Only an instruction set with a base ISA (i or e)
has the rv32/rv64 prefix, for others it only lists extensions, like m2p0_zmmul1p0.
Note that this constant is not supposed to be specified explicitly.
Required Associated Types§
Sourcetype Hart: HartConfig
type Hart: HartConfig
Hart configuration of the implementation
Required Methods§
Sourcefn try_decode(instruction: u32) -> Option<Self>
fn try_decode(instruction: u32) -> Option<Self>
Try to decode a single valid instruction
Provided Methods§
Sourcefn implements_extension<E>() -> boolwhere
E: Instruction<Hart = Self::Hart>,
fn implements_extension<E>() -> boolwhere
E: Instruction<Hart = Self::Hart>,
Checks whether this instruction implements the given extension, see
Self::IMPLEMENTED_EXTENSIONS for details
Dyn Compatibility§
This trait is not dyn compatible.
In older versions of Rust, dyn compatibility was called "object safety".
Implementors§
§impl<Reg, Hart> Instruction for Rv32AInstruction<Hart>
impl<Reg, Hart> Instruction for Rv32AInstruction<Hart>
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const ALIGNMENT: u8
type Hart = Hart
§impl<Reg, Hart> Instruction for Rv32BInstruction<Hart>
impl<Reg, Hart> Instruction for Rv32BInstruction<Hart>
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const ALIGNMENT: u8
type Hart = Hart
§impl<Reg, Hart> Instruction for Rv32Instruction<Hart>
impl<Reg, Hart> Instruction for Rv32Instruction<Hart>
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const ALIGNMENT: u8
type Hart = Hart
§impl<Reg, Hart> Instruction for Rv32MInstruction<Hart>
impl<Reg, Hart> Instruction for Rv32MInstruction<Hart>
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const ALIGNMENT: u8
type Hart = Hart
§impl<Reg, Hart> Instruction for Rv32ZaamoInstruction<Hart>
impl<Reg, Hart> Instruction for Rv32ZaamoInstruction<Hart>
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const ALIGNMENT: u8
type Hart = Hart
§impl<Reg, Hart> Instruction for Rv32ZabhaInstruction<Hart>
impl<Reg, Hart> Instruction for Rv32ZabhaInstruction<Hart>
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const ALIGNMENT: u8
type Hart = Hart
§impl<Reg, Hart> Instruction for Rv32ZacasInstruction<Hart>
impl<Reg, Hart> Instruction for Rv32ZacasInstruction<Hart>
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const ALIGNMENT: u8
type Hart = Hart
§impl<Reg, Hart> Instruction for Rv32ZalasrInstruction<Hart>
impl<Reg, Hart> Instruction for Rv32ZalasrInstruction<Hart>
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const ALIGNMENT: u8
type Hart = Hart
§impl<Reg, Hart> Instruction for Rv32ZalrscInstruction<Hart>
impl<Reg, Hart> Instruction for Rv32ZalrscInstruction<Hart>
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const ALIGNMENT: u8
type Hart = Hart
§impl<Reg, Hart> Instruction for Rv32ZbaInstruction<Hart>
impl<Reg, Hart> Instruction for Rv32ZbaInstruction<Hart>
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const ALIGNMENT: u8
type Hart = Hart
§impl<Reg, Hart> Instruction for Rv32ZbbInstruction<Hart>
impl<Reg, Hart> Instruction for Rv32ZbbInstruction<Hart>
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const ALIGNMENT: u8
type Hart = Hart
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const ALIGNMENT: u8
type Hart = Hart
§impl<Reg, Hart> Instruction for Rv32ZbcInstruction<Hart>
impl<Reg, Hart> Instruction for Rv32ZbcInstruction<Hart>
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const ALIGNMENT: u8
type Hart = Hart
§impl<Reg, Hart> Instruction for Rv32ZbkbInstruction<Hart>
impl<Reg, Hart> Instruction for Rv32ZbkbInstruction<Hart>
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const ALIGNMENT: u8
type Hart = Hart
§impl<Reg, Hart> Instruction for Rv32ZbkcInstruction<Hart>
impl<Reg, Hart> Instruction for Rv32ZbkcInstruction<Hart>
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const ALIGNMENT: u8
type Hart = Hart
§impl<Reg, Hart> Instruction for Rv32ZbkxInstruction<Hart>
impl<Reg, Hart> Instruction for Rv32ZbkxInstruction<Hart>
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const ALIGNMENT: u8
type Hart = Hart
§impl<Reg, Hart> Instruction for Rv32ZbsInstruction<Hart>
impl<Reg, Hart> Instruction for Rv32ZbsInstruction<Hart>
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const ALIGNMENT: u8
type Hart = Hart
§impl<Reg, Hart> Instruction for Rv32ZcaInstruction<Hart>
impl<Reg, Hart> Instruction for Rv32ZcaInstruction<Hart>
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const ALIGNMENT: u8
type Hart = Hart
§impl<Reg, Hart> Instruction for Rv32ZcbInstruction<Hart>
impl<Reg, Hart> Instruction for Rv32ZcbInstruction<Hart>
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const ALIGNMENT: u8
type Hart = Hart
§impl<Reg, Hart> Instruction for Rv32ZcmpInstruction<Hart>
impl<Reg, Hart> Instruction for Rv32ZcmpInstruction<Hart>
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const ALIGNMENT: u8
type Hart = Hart
§impl<Reg, Hart> Instruction for Rv32ZknInstruction<Hart>
impl<Reg, Hart> Instruction for Rv32ZknInstruction<Hart>
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const ALIGNMENT: u8
type Hart = Hart
§impl<Reg, Hart> Instruction for Rv32ZkndInstruction<Hart>
Encoding layout (R-type, opcode 0x33, funct3 0x0):
impl<Reg, Hart> Instruction for Rv32ZkndInstruction<Hart>
Encoding layout (R-type, opcode 0x33, funct3 0x0):
[31:30] bs - 2-bit byte select
[29:25] funct5 - 0b1_0101 (aes32dsi) / 0b1_0111 (aes32dsmi)
[24:20] rs2
[19:15] rs1
[14:12] funct3 - 0b000
[11:7] rd
[6:0] opcode - 0b011_0011 (OP)Ratified match/mask values (from riscv-opcodes): MATCH_AES32DSI = 0x2a00_0033, MASK_AES32DSI = 0x3e00_707f MATCH_AES32DSMI = 0x2e00_0033, MASK_AES32DSMI = 0x3e00_707f
rd and rs1 are independent fields. The assembler convention places
the accumulator in both rd and rs1 (the rt pattern), but the hardware
does not require rd == rs1 and the decoder must not enforce it.
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const ALIGNMENT: u8
type Hart = Hart
§impl<Reg, Hart> Instruction for Rv32ZkneInstruction<Hart>
Encoding layout (R-type, opcode 0x33, funct3 0x0):
impl<Reg, Hart> Instruction for Rv32ZkneInstruction<Hart>
Encoding layout (R-type, opcode 0x33, funct3 0x0):
[31:30] bs - 2-bit byte select
[29:25] funct5 - 0b1_0001 (aes32esi) / 0b1_0011 (aes32esmi)
[24:20] rs2
[19:15] rs1
[14:12] funct3 - 0b000
[11:7] rd
[6:0] opcode - 0b011_0011 (OP)Ratified match/mask values (from riscv-opcodes): MATCH_AES32ESI = 0x2200_0033, MASK_AES32ESI = 0x3e00_707f MATCH_AES32ESMI = 0x2600_0033, MASK_AES32ESMI = 0x3e00_707f
rd and rs1 are independent fields. The assembler convention places
the accumulator in both rd and rs1 (the rt pattern), but the hardware
does not require rd == rs1 and the decoder must not enforce it.