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Rv64BInstruction

ab_riscv_primitives::instructions::rv64::b

Enum Rv64BInstruction

pub enum Rv64BInstruction<Reg> {
Show 40 variants    AddUw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sh1add {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sh1addUw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sh2add {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sh2addUw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sh3add {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sh3addUw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    SlliUw {
        rd: Reg,
        rs1: Reg,
        shamt: u8,
    },
    Andn {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Orn {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Xnor {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Clz {
        rd: Reg,
        rs1: Reg,
    },
    Clzw {
        rd: Reg,
        rs1: Reg,
    },
    Ctz {
        rd: Reg,
        rs1: Reg,
    },
    Ctzw {
        rd: Reg,
        rs1: Reg,
    },
    Cpop {
        rd: Reg,
        rs1: Reg,
    },
    Cpopw {
        rd: Reg,
        rs1: Reg,
    },
    Max {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Maxu {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Min {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Minu {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sextb {
        rd: Reg,
        rs1: Reg,
    },
    Sexth {
        rd: Reg,
        rs1: Reg,
    },
    Zexth {
        rd: Reg,
        rs1: Reg,
    },
    Rol {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Rolw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Ror {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Rori {
        rd: Reg,
        rs1: Reg,
        shamt: u8,
    },
    Roriw {
        rd: Reg,
        rs1: Reg,
        shamt: u8,
    },
    Rorw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Orcb {
        rd: Reg,
        rs1: Reg,
    },
    Rev8 {
        rd: Reg,
        rs1: Reg,
    },
    Bset {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Bseti {
        rd: Reg,
        rs1: Reg,
        shamt: u8,
    },
    Bclr {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Bclri {
        rd: Reg,
        rs1: Reg,
        shamt: u8,
    },
    Binv {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Binvi {
        rd: Reg,
        rs1: Reg,
        shamt: u8,
    },
    Bext {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Bexti {
        rd: Reg,
        rs1: Reg,
        shamt: u8,
    },
}

Variants§

AddUw

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Sh1add

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Sh1addUw

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Sh2add

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Sh2addUw

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Sh3add

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Sh3addUw

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

SlliUw

Fields

§rd: Reg

§rs1: Reg

§shamt: u8

Andn

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Orn

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Xnor

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Clz

Fields

§rd: Reg

§rs1: Reg

Clzw

Fields

§rd: Reg

§rs1: Reg

Ctz

Fields

§rd: Reg

§rs1: Reg

Ctzw

Fields

§rd: Reg

§rs1: Reg

Cpop

Fields

§rd: Reg

§rs1: Reg

Cpopw

Fields

§rd: Reg

§rs1: Reg

Max

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Maxu

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Min

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Minu

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Sextb

Fields

§rd: Reg

§rs1: Reg

Sexth

Fields

§rd: Reg

§rs1: Reg

Zexth

Fields

§rd: Reg

§rs1: Reg

Rol

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Rolw

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Ror

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Rori

Fields

§rd: Reg

§rs1: Reg

§shamt: u8

Roriw

Fields

§rd: Reg

§rs1: Reg

§shamt: u8

Rorw

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Orcb

Fields

§rd: Reg

§rs1: Reg

Rev8

Fields

§rd: Reg

§rs1: Reg

Bset

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Bseti

Fields

§rd: Reg

§rs1: Reg

§shamt: u8

Bclr

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Bclri

Fields

§rd: Reg

§rs1: Reg

§shamt: u8

Binv

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Binvi

Fields

§rd: Reg

§rs1: Reg

§shamt: u8

Bext

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Bexti

Fields

§rd: Reg

§rs1: Reg

§shamt: u8

Trait Implementations§

impl<Reg: Clone> Clone for Rv64BInstruction<Reg>

fn clone(&self) -> Rv64BInstruction<Reg>

Returns a duplicate of the value. Read more

1.0.0 · Source§

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more

impl<Reg: Debug> Debug for Rv64BInstruction<Reg>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more

impl<Reg> Display for Rv64BInstruction<Reg>
where Reg: Display + Copy,

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more

impl<Reg> Instruction for Rv64BInstruction<Reg>
where Reg: Register<Type = u64>,

type Reg = Reg

A register type used by the instruction

fn try_decode(instruction: u32) -> Option<Self>

Try to decode a single valid instruction

fn alignment() -> u8

Instruction alignment in bytes

fn size(&self) -> u8

Instruction size in bytes

impl<Reg: PartialEq> PartialEq for Rv64BInstruction<Reg>

fn eq(&self, other: &Rv64BInstruction<Reg>) -> bool

Tests for self and other values to be equal, and is used by ==.

1.0.0 · Source§

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl<Reg: Copy> Copy for Rv64BInstruction<Reg>

impl<Reg: Eq> Eq for Rv64BInstruction<Reg>

impl<Reg> StructuralPartialEq for Rv64BInstruction<Reg>

Auto Trait Implementations§

impl<Reg> Freeze for Rv64BInstruction<Reg>
where Reg: Freeze,

impl<Reg> RefUnwindSafe for Rv64BInstruction<Reg>
where Reg: RefUnwindSafe,

impl<Reg> Send for Rv64BInstruction<Reg>
where Reg: Send,

impl<Reg> Sync for Rv64BInstruction<Reg>
where Reg: Sync,

impl<Reg> Unpin for Rv64BInstruction<Reg>
where Reg: Unpin,

impl<Reg> UnwindSafe for Rv64BInstruction<Reg>
where Reg: UnwindSafe,

Blanket Implementations§

impl<T> Any for T
where T: 'static + ?Sized,

fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more

impl<T> Borrow<T> for T
where T: ?Sized,

fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more

impl<T> BorrowMut<T> for T
where T: ?Sized,

fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more

impl<T> CloneToUninit for T
where T: Clone,

unsafe fn clone_to_uninit(&self, dest: *mut u8)

🔬This is a nightly-only experimental API. (clone_to_uninit)

Performs copy-assignment from self to dest. Read more

impl<T> From<T> for T

fn from(t: T) -> T

Returns the argument unchanged.

impl<T, U> Into<U> for T
where U: From<T>,

fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

impl<T> ToOwned for T
where T: Clone,

type Owned = T

The resulting type after obtaining ownership.

fn to_owned(&self) -> T

Creates owned data from borrowed data, usually by cloning. Read more

fn clone_into(&self, target: &mut T)

Uses borrowed data to replace owned data, usually by cloning. Read more

impl<T> ToString for T
where T: Display + ?Sized,

fn to_string(&self) -> String

Converts the given value to a String. Read more

impl<T, U> TryFrom<U> for T
where U: Into<T>,

type Error = Infallible

The type returned in the event of a conversion error.

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.

impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.