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Rv64Zve64xInstruction

ab_riscv_primitives::instructions::rv64::v::zve64x

Enum Rv64Zve64xInstruction 

Source 
pub enum Rv64Zve64xInstruction<Reg> {

Show 217 variants    Vsetvli {
        rd: Reg,
        rs1: Reg,
        vtypei: u16,
    },
    Vsetivli {
        rd: Reg,
        uimm: u8,
        vtypei: u16,
    },
    Vsetvl {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Vle {
        vd: VReg,
        rs1: Reg,
        vm: bool,
        eew: Eew,
    },
    Vleff {
        vd: VReg,
        rs1: Reg,
        vm: bool,
        eew: Eew,
    },
    Vlm {
        vd: VReg,
        rs1: Reg,
    },
    Vlse {
        vd: VReg,
        rs1: Reg,
        rs2: Reg,
        vm: bool,
        eew: Eew,
    },
    Vluxei {
        vd: VReg,
        rs1: Reg,
        vs2: VReg,
        vm: bool,
        eew: Eew,
    },
    Vloxei {
        vd: VReg,
        rs1: Reg,
        vs2: VReg,
        vm: bool,
        eew: Eew,
    },
    Vlr {
        vd: VReg,
        rs1: Reg,
        nreg: u8,
        eew: Eew,
    },
    Vlseg {
        vd: VReg,
        rs1: Reg,
        vm: bool,
        eew: Eew,
        nf: u8,
    },
    Vlsegff {
        vd: VReg,
        rs1: Reg,
        vm: bool,
        eew: Eew,
        nf: u8,
    },
    Vlsseg {
        vd: VReg,
        rs1: Reg,
        rs2: Reg,
        vm: bool,
        eew: Eew,
        nf: u8,
    },
    Vluxseg {
        vd: VReg,
        rs1: Reg,
        vs2: VReg,
        vm: bool,
        eew: Eew,
        nf: u8,
    },
    Vloxseg {
        vd: VReg,
        rs1: Reg,
        vs2: VReg,
        vm: bool,
        eew: Eew,
        nf: u8,
    },
    Vse {
        vs3: VReg,
        rs1: Reg,
        vm: bool,
        eew: Eew,
    },
    Vsm {
        vs3: VReg,
        rs1: Reg,
    },
    Vsse {
        vs3: VReg,
        rs1: Reg,
        rs2: Reg,
        vm: bool,
        eew: Eew,
    },
    Vsuxei {
        vs3: VReg,
        rs1: Reg,
        vs2: VReg,
        vm: bool,
        eew: Eew,
    },
    Vsoxei {
        vs3: VReg,
        rs1: Reg,
        vs2: VReg,
        vm: bool,
        eew: Eew,
    },
    Vsr {
        vs3: VReg,
        rs1: Reg,
        nreg: u8,
    },
    Vsseg {
        vs3: VReg,
        rs1: Reg,
        vm: bool,
        eew: Eew,
        nf: u8,
    },
    Vssseg {
        vs3: VReg,
        rs1: Reg,
        rs2: Reg,
        vm: bool,
        eew: Eew,
        nf: u8,
    },
    Vsuxseg {
        vs3: VReg,
        rs1: Reg,
        vs2: VReg,
        vm: bool,
        eew: Eew,
        nf: u8,
    },
    Vsoxseg {
        vs3: VReg,
        rs1: Reg,
        vs2: VReg,
        vm: bool,
        eew: Eew,
        nf: u8,
    },
    VaddVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VaddVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VaddVi {
        vd: VReg,
        vs2: VReg,
        imm: i8,
        vm: bool,
    },
    VsubVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VsubVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VrsubVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VrsubVi {
        vd: VReg,
        vs2: VReg,
        imm: i8,
        vm: bool,
    },
    VandVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VandVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VandVi {
        vd: VReg,
        vs2: VReg,
        imm: i8,
        vm: bool,
    },
    VorVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VorVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VorVi {
        vd: VReg,
        vs2: VReg,
        imm: i8,
        vm: bool,
    },
    VxorVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VxorVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VxorVi {
        vd: VReg,
        vs2: VReg,
        imm: i8,
        vm: bool,
    },
    VsllVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VsllVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VsllVi {
        vd: VReg,
        vs2: VReg,
        uimm: u8,
        vm: bool,
    },
    VsrlVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VsrlVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VsrlVi {
        vd: VReg,
        vs2: VReg,
        uimm: u8,
        vm: bool,
    },
    VsraVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VsraVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VsraVi {
        vd: VReg,
        vs2: VReg,
        uimm: u8,
        vm: bool,
    },
    VminuVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VminuVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VminVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VminVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VmaxuVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VmaxuVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VmaxVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VmaxVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VmseqVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VmseqVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VmseqVi {
        vd: VReg,
        vs2: VReg,
        imm: i8,
        vm: bool,
    },
    VmsneVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VmsneVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VmsneVi {
        vd: VReg,
        vs2: VReg,
        imm: i8,
        vm: bool,
    },
    VmsltuVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VmsltuVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VmsltVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VmsltVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VmsleuVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VmsleuVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VmsleuVi {
        vd: VReg,
        vs2: VReg,
        imm: i8,
        vm: bool,
    },
    VmsleVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VmsleVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VmsleVi {
        vd: VReg,
        vs2: VReg,
        imm: i8,
        vm: bool,
    },
    VmsgtuVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VmsgtuVi {
        vd: VReg,
        vs2: VReg,
        imm: i8,
        vm: bool,
    },
    VmsgtVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VmsgtVi {
        vd: VReg,
        vs2: VReg,
        imm: i8,
        vm: bool,
    },
    VmulVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VmulVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VmulhVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VmulhVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VmulhuVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VmulhuVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VmulhsuVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VmulhsuVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VdivuVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VdivuVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VdivVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VdivVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VremuVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VremuVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VremVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VremVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VwmulVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VwmulVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VwmuluVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VwmuluVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VwmulsuVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VwmulsuVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VmaccVv {
        vd: VReg,
        vs1: VReg,
        vs2: VReg,
        vm: bool,
    },
    VmaccVx {
        vd: VReg,
        rs1: Reg,
        vs2: VReg,
        vm: bool,
    },
    VnmsacVv {
        vd: VReg,
        vs1: VReg,
        vs2: VReg,
        vm: bool,
    },
    VnmsacVx {
        vd: VReg,
        rs1: Reg,
        vs2: VReg,
        vm: bool,
    },
    VmaddVv {
        vd: VReg,
        vs1: VReg,
        vs2: VReg,
        vm: bool,
    },
    VmaddVx {
        vd: VReg,
        rs1: Reg,
        vs2: VReg,
        vm: bool,
    },
    VnmsubVv {
        vd: VReg,
        vs1: VReg,
        vs2: VReg,
        vm: bool,
    },
    VnmsubVx {
        vd: VReg,
        rs1: Reg,
        vs2: VReg,
        vm: bool,
    },
    VwmaccuVv {
        vd: VReg,
        vs1: VReg,
        vs2: VReg,
        vm: bool,
    },
    VwmaccuVx {
        vd: VReg,
        rs1: Reg,
        vs2: VReg,
        vm: bool,
    },
    VwmaccVv {
        vd: VReg,
        vs1: VReg,
        vs2: VReg,
        vm: bool,
    },
    VwmaccVx {
        vd: VReg,
        rs1: Reg,
        vs2: VReg,
        vm: bool,
    },
    VwmaccsuVv {
        vd: VReg,
        vs1: VReg,
        vs2: VReg,
        vm: bool,
    },
    VwmaccsuVx {
        vd: VReg,
        rs1: Reg,
        vs2: VReg,
        vm: bool,
    },
    VwmaccusVx {
        vd: VReg,
        rs1: Reg,
        vs2: VReg,
        vm: bool,
    },
    VwadduVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VwadduVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VwaddVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VwaddVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VwsubuVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VwsubuVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VwsubVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VwsubVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VwadduWv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VwadduWx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VwaddWv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VwaddWx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VwsubuWv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VwsubuWx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VwsubWv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VwsubWx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VnsrlWv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VnsrlWx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VnsrlWi {
        vd: VReg,
        vs2: VReg,
        uimm: u8,
        vm: bool,
    },
    VnsraWv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VnsraWx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VnsraWi {
        vd: VReg,
        vs2: VReg,
        uimm: u8,
        vm: bool,
    },
    VzextVf2 {
        vd: VReg,
        vs2: VReg,
        vm: bool,
    },
    VzextVf4 {
        vd: VReg,
        vs2: VReg,
        vm: bool,
    },
    VzextVf8 {
        vd: VReg,
        vs2: VReg,
        vm: bool,
    },
    VsextVf2 {
        vd: VReg,
        vs2: VReg,
        vm: bool,
    },
    VsextVf4 {
        vd: VReg,
        vs2: VReg,
        vm: bool,
    },
    VsextVf8 {
        vd: VReg,
        vs2: VReg,
        vm: bool,
    },
    VsadduVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VsadduVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VsadduVi {
        vd: VReg,
        vs2: VReg,
        imm: i8,
        vm: bool,
    },
    VsaddVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VsaddVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VsaddVi {
        vd: VReg,
        vs2: VReg,
        imm: i8,
        vm: bool,
    },
    VssubuVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VssubuVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VssubVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VssubVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VaadduVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VaadduVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VaaddVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VaaddVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VasubuVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VasubuVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VasubVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VasubVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VsmulVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VsmulVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VssrlVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VssrlVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VssrlVi {
        vd: VReg,
        vs2: VReg,
        imm: u8,
        vm: bool,
    },
    VssraVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VssraVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VssraVi {
        vd: VReg,
        vs2: VReg,
        imm: u8,
        vm: bool,
    },
    VnclipuWv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VnclipuWx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VnclipuWi {
        vd: VReg,
        vs2: VReg,
        imm: u8,
        vm: bool,
    },
    VnclipWv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VnclipWx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VnclipWi {
        vd: VReg,
        vs2: VReg,
        imm: u8,
        vm: bool,
    },
    Vmandn {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
    },
    Vmand {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
    },
    Vmor {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
    },
    Vmxor {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
    },
    Vmorn {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
    },
    Vmnand {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
    },
    Vmnor {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
    },
    Vmxnor {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
    },
    Vcpop {
        rd: Reg,
        vs2: VReg,
        vm: bool,
    },
    Vfirst {
        rd: Reg,
        vs2: VReg,
        vm: bool,
    },
    Vmsbf {
        vd: VReg,
        vs2: VReg,
        vm: bool,
    },
    Vmsof {
        vd: VReg,
        vs2: VReg,
        vm: bool,
    },
    Vmsif {
        vd: VReg,
        vs2: VReg,
        vm: bool,
    },
    Viota {
        vd: VReg,
        vs2: VReg,
        vm: bool,
    },
    Vid {
        vd: VReg,
        vm: bool,
    },
    Vredsum {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    Vredand {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    Vredor {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    Vredxor {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    Vredminu {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    Vredmin {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    Vredmaxu {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    Vredmax {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    Vwredsumu {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    Vwredsum {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VmvXS {
        rd: Reg,
        vs2: VReg,
    },
    VmvSX {
        vd: VReg,
        rs1: Reg,
    },
    VslideupVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VslideupVi {
        vd: VReg,
        vs2: VReg,
        uimm: u8,
        vm: bool,
    },
    VslidedownVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VslidedownVi {
        vd: VReg,
        vs2: VReg,
        uimm: u8,
        vm: bool,
    },
    Vslide1upVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    Vslide1downVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VrgatherVv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VrgatherVx {
        vd: VReg,
        vs2: VReg,
        rs1: Reg,
        vm: bool,
    },
    VrgatherVi {
        vd: VReg,
        vs2: VReg,
        uimm: u8,
        vm: bool,
    },
    Vrgatherei16Vv {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
        vm: bool,
    },
    VcompressVm {
        vd: VReg,
        vs2: VReg,
        vs1: VReg,
    },
    Vmv1rV {
        vd: VReg,
        vs2: VReg,
    },
    Vmv2rV {
        vd: VReg,
        vs2: VReg,
    },
    Vmv4rV {
        vd: VReg,
        vs2: VReg,
    },
    Vmv8rV {
        vd: VReg,
        vs2: VReg,
    },

}

Variants§

§

Vsetvli

Set vector length and type from GPR

vsetvli rd, rs1, vtypei rd = new vl, rs1 = AVL, vtypei = new vtype setting (11-bit immediate)

Fields

§rd: Reg
§rs1: Reg
§vtypei: u16
§

Vsetivli

Set vector length and type from immediate AVL

vsetivli rd, uimm, vtypei rd = new vl, uimm[4:0] = AVL, vtypei = new vtype setting (10-bit immediate)

Fields

§rd: Reg
§uimm: u8
§vtypei: u16
§

Vsetvl

Set vector length and type from GPRs

vsetvl rd, rs1, rs2 rd = new vl, rs1 = AVL, rs2 = new vtype value

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Vle

Unit-stride load: vle{eew}.v vd, (rs1), vm

mop=00, lumop=00000, nf=000

Fields

§vd: VReg
§rs1: Reg
§vm: bool
§eew: Eew
§

Vleff

Unit-stride fault-only-first load: vle{eew}ff.v vd, (rs1), vm

mop=00, lumop=10000, nf=000

Fields

§vd: VReg
§rs1: Reg
§vm: bool
§eew: Eew
§

Vlm

Unit-stride mask load: vlm.v vd, (rs1)

mop=00, lumop=01011, nf=000, eew=e8, vm=1

Fields

§vd: VReg
§rs1: Reg
§

Vlse

Strided load: vlse{eew}.v vd, (rs1), rs2, vm

mop=10, nf=000

Fields

§vd: VReg
§rs1: Reg
§rs2: Reg
§vm: bool
§eew: Eew
§

Vluxei

Indexed-unordered load: vluxei{eew}.v vd, (rs1), vs2, vm

mop=01, nf=000. eew is the index element width.

Fields

§vd: VReg
§rs1: Reg
§vs2: VReg
§vm: bool
§eew: Eew
§

Vloxei

Indexed-ordered load: vloxei{eew}.v vd, (rs1), vs2, vm

mop=11, nf=000. eew is the index element width.

Fields

§vd: VReg
§rs1: Reg
§vs2: VReg
§vm: bool
§eew: Eew
§

Vlr

Whole-register load: vl{nreg}re{eew}.v vd, (rs1)

mop=00, lumop=01000, vm=1. nreg must be 1, 2, 4, or 8.

Fields

§vd: VReg
§rs1: Reg
§nreg: u8
§eew: Eew
§

Vlseg

Unit-stride segment load: vlseg{nf}e{eew}.v vd, (rs1), vm

mop=00, lumop=00000, nf>0

Fields

§vd: VReg
§rs1: Reg
§vm: bool
§eew: Eew
§nf: u8
§

Vlsegff

Unit-stride fault-only-first segment load: vlseg{nf}e{eew}ff.v vd, (rs1), vm

mop=00, lumop=10000, nf>0

Fields

§vd: VReg
§rs1: Reg
§vm: bool
§eew: Eew
§nf: u8
§

Vlsseg

Strided segment load: vlsseg{nf}e{eew}.v vd, (rs1), rs2, vm

mop=10, nf>0

Fields

§vd: VReg
§rs1: Reg
§rs2: Reg
§vm: bool
§eew: Eew
§nf: u8
§

Vluxseg

Indexed-unordered segment load: vluxseg{nf}ei{eew}.v vd, (rs1), vs2, vm

mop=01, nf>0

Fields

§vd: VReg
§rs1: Reg
§vs2: VReg
§vm: bool
§eew: Eew
§nf: u8
§

Vloxseg

Indexed-ordered segment load: vloxseg{nf}ei{eew}.v vd, (rs1), vs2, vm

mop=11, nf>0

Fields

§vd: VReg
§rs1: Reg
§vs2: VReg
§vm: bool
§eew: Eew
§nf: u8
§

Vse

Unit-stride store: vse{eew}.v vs3, (rs1), vm

mop=00, sumop=00000, nf=000

Fields

§vs3: VReg
§rs1: Reg
§vm: bool
§eew: Eew
§

Vsm

Unit-stride mask store: vsm.v vs3, (rs1)

mop=00, sumop=01011, nf=000, eew=e8, vm=1

Fields

§vs3: VReg
§rs1: Reg
§

Vsse

Strided store: vsse{eew}.v vs3, (rs1), rs2, vm

mop=10, nf=000

Fields

§vs3: VReg
§rs1: Reg
§rs2: Reg
§vm: bool
§eew: Eew
§

Vsuxei

Indexed-unordered store: vsuxei{eew}.v vs3, (rs1), vs2, vm

mop=01, nf=000. eew is the index element width.

Fields

§vs3: VReg
§rs1: Reg
§vs2: VReg
§vm: bool
§eew: Eew
§

Vsoxei

Indexed-ordered store: vsoxei{eew}.v vs3, (rs1), vs2, vm

mop=11, nf=000. eew is the index element width.

Fields

§vs3: VReg
§rs1: Reg
§vs2: VReg
§vm: bool
§eew: Eew
§

Vsr

Whole-register store: vs{nreg}r.v vs3, (rs1)

mop=00, sumop=01000, vm=1. nreg must be 1, 2, 4, or 8.

Fields

§vs3: VReg
§rs1: Reg
§nreg: u8
§

Vsseg

Unit-stride segment store: vsseg{nf}e{eew}.v vs3, (rs1), vm

mop=00, sumop=00000, nf>0

Fields

§vs3: VReg
§rs1: Reg
§vm: bool
§eew: Eew
§nf: u8
§

Vssseg

Strided segment store: vssseg{nf}e{eew}.v vs3, (rs1), rs2, vm

mop=10, nf>0

Fields

§vs3: VReg
§rs1: Reg
§rs2: Reg
§vm: bool
§eew: Eew
§nf: u8
§

Vsuxseg

Indexed-unordered segment store: vsuxseg{nf}ei{eew}.v vs3, (rs1), vs2, vm

mop=01, nf>0

Fields

§vs3: VReg
§rs1: Reg
§vs2: VReg
§vm: bool
§eew: Eew
§nf: u8
§

Vsoxseg

Indexed-ordered segment store: vsoxseg{nf}ei{eew}.v vs3, (rs1), vs2, vm

mop=11, nf>0

Fields

§vs3: VReg
§rs1: Reg
§vs2: VReg
§vm: bool
§eew: Eew
§nf: u8
§

VaddVv

vadd.vv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VaddVx

vadd.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VaddVi

vadd.vi vd, vs2, imm, vm

Fields

§vd: VReg
§vs2: VReg
§imm: i8
§vm: bool
§

VsubVv

vsub.vv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VsubVx

vsub.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VrsubVx

vrsub.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VrsubVi

vrsub.vi vd, vs2, imm, vm

Fields

§vd: VReg
§vs2: VReg
§imm: i8
§vm: bool
§

VandVv

vand.vv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VandVx

vand.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VandVi

vand.vi vd, vs2, imm, vm

Fields

§vd: VReg
§vs2: VReg
§imm: i8
§vm: bool
§

VorVv

vor.vv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VorVx

vor.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VorVi

vor.vi vd, vs2, imm, vm

Fields

§vd: VReg
§vs2: VReg
§imm: i8
§vm: bool
§

VxorVv

vxor.vv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VxorVx

vxor.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VxorVi

vxor.vi vd, vs2, imm, vm

Fields

§vd: VReg
§vs2: VReg
§imm: i8
§vm: bool
§

VsllVv

vsll.vv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VsllVx

vsll.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VsllVi

vsll.vi vd, vs2, uimm, vm

Fields

§vd: VReg
§vs2: VReg
§uimm: u8
§vm: bool
§

VsrlVv

vsrl.vv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VsrlVx

vsrl.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VsrlVi

vsrl.vi vd, vs2, uimm, vm

Fields

§vd: VReg
§vs2: VReg
§uimm: u8
§vm: bool
§

VsraVv

vsra.vv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VsraVx

vsra.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VsraVi

vsra.vi vd, vs2, uimm, vm

Fields

§vd: VReg
§vs2: VReg
§uimm: u8
§vm: bool
§

VminuVv

vminu.vv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VminuVx

vminu.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VminVv

vmin.vv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VminVx

vmin.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VmaxuVv

vmaxu.vv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VmaxuVx

vmaxu.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VmaxVv

vmax.vv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VmaxVx

vmax.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VmseqVv

vmseq.vv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VmseqVx

vmseq.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VmseqVi

vmseq.vi vd, vs2, imm, vm

Fields

§vd: VReg
§vs2: VReg
§imm: i8
§vm: bool
§

VmsneVv

vmsne.vv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VmsneVx

vmsne.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VmsneVi

vmsne.vi vd, vs2, imm, vm

Fields

§vd: VReg
§vs2: VReg
§imm: i8
§vm: bool
§

VmsltuVv

vmsltu.vv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VmsltuVx

vmsltu.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VmsltVv

vmslt.vv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VmsltVx

vmslt.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VmsleuVv

vmsleu.vv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VmsleuVx

vmsleu.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VmsleuVi

vmsleu.vi vd, vs2, imm, vm

Fields

§vd: VReg
§vs2: VReg
§imm: i8
§vm: bool
§

VmsleVv

vmsle.vv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VmsleVx

vmsle.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VmsleVi

vmsle.vi vd, vs2, imm, vm

Fields

§vd: VReg
§vs2: VReg
§imm: i8
§vm: bool
§

VmsgtuVx

vmsgtu.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VmsgtuVi

vmsgtu.vi vd, vs2, imm, vm

Fields

§vd: VReg
§vs2: VReg
§imm: i8
§vm: bool
§

VmsgtVx

vmsgt.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VmsgtVi

vmsgt.vi vd, vs2, imm, vm

Fields

§vd: VReg
§vs2: VReg
§imm: i8
§vm: bool
§

VmulVv

vmul.vv vd, vs2, vs1, vm - signed multiply, low bits

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VmulVx

vmul.vx vd, vs2, rs1, vm - signed multiply, low bits

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VmulhVv

vmulh.vv vd, vs2, vs1, vm - signed×signed multiply, high bits

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VmulhVx

vmulh.vx vd, vs2, rs1, vm - signed×signed multiply, high bits

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VmulhuVv

vmulhu.vv vd, vs2, vs1, vm - unsigned×unsigned multiply, high bits

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VmulhuVx

vmulhu.vx vd, vs2, rs1, vm - unsigned×unsigned multiply, high bits

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VmulhsuVv

vmulhsu.vv vd, vs2, vs1, vm - signed×unsigned multiply, high bits

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VmulhsuVx

vmulhsu.vx vd, vs2, rs1, vm - signed×unsigned multiply, high bits

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VdivuVv

vdivu.vv vd, vs2, vs1, vm - unsigned divide

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VdivuVx

vdivu.vx vd, vs2, rs1, vm - unsigned divide

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VdivVv

vdiv.vv vd, vs2, vs1, vm - signed divide

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VdivVx

vdiv.vx vd, vs2, rs1, vm - signed divide

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VremuVv

vremu.vv vd, vs2, vs1, vm - unsigned remainder

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VremuVx

vremu.vx vd, vs2, rs1, vm - unsigned remainder

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VremVv

vrem.vv vd, vs2, vs1, vm - signed remainder

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VremVx

vrem.vx vd, vs2, rs1, vm - signed remainder

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VwmulVv

vwmul.vv vd, vs2, vs1, vm - signed widening multiply

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VwmulVx

vwmul.vx vd, vs2, rs1, vm - signed widening multiply

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VwmuluVv

vwmulu.vv vd, vs2, vs1, vm - unsigned widening multiply

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VwmuluVx

vwmulu.vx vd, vs2, rs1, vm - unsigned widening multiply

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VwmulsuVv

vwmulsu.vv vd, vs2, vs1, vm - signed×unsigned widening multiply

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VwmulsuVx

vwmulsu.vx vd, vs2, rs1, vm - signed×unsigned widening multiply

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VmaccVv

vmacc.vv vd, vs1, vs2, vm - vd = vd + vs1 * vs2

Fields

§vd: VReg
§vs1: VReg
§vs2: VReg
§vm: bool
§

VmaccVx

vmacc.vx vd, rs1, vs2, vm - vd = vd + rs1 * vs2

Fields

§vd: VReg
§rs1: Reg
§vs2: VReg
§vm: bool
§

VnmsacVv

vnmsac.vv vd, vs1, vs2, vm - vd = vd - vs1 * vs2

Fields

§vd: VReg
§vs1: VReg
§vs2: VReg
§vm: bool
§

VnmsacVx

vnmsac.vx vd, rs1, vs2, vm - vd = vd - rs1 * vs2

Fields

§vd: VReg
§rs1: Reg
§vs2: VReg
§vm: bool
§

VmaddVv

vmadd.vv vd, vs1, vs2, vm - vd = vs1 * vd + vs2

Fields

§vd: VReg
§vs1: VReg
§vs2: VReg
§vm: bool
§

VmaddVx

vmadd.vx vd, rs1, vs2, vm - vd = rs1 * vd + vs2

Fields

§vd: VReg
§rs1: Reg
§vs2: VReg
§vm: bool
§

VnmsubVv

vnmsub.vv vd, vs1, vs2, vm - vd = -(vs1 * vd - vs2)

Fields

§vd: VReg
§vs1: VReg
§vs2: VReg
§vm: bool
§

VnmsubVx

vnmsub.vx vd, rs1, vs2, vm - vd = -(rs1 * vd - vs2)

Fields

§vd: VReg
§rs1: Reg
§vs2: VReg
§vm: bool
§

VwmaccuVv

vwmaccu.vv vd, vs1, vs2, vm - unsigned widening multiply-add

Fields

§vd: VReg
§vs1: VReg
§vs2: VReg
§vm: bool
§

VwmaccuVx

vwmaccu.vx vd, rs1, vs2, vm - unsigned widening multiply-add

Fields

§vd: VReg
§rs1: Reg
§vs2: VReg
§vm: bool
§

VwmaccVv

vwmacc.vv vd, vs1, vs2, vm - signed widening multiply-add

Fields

§vd: VReg
§vs1: VReg
§vs2: VReg
§vm: bool
§

VwmaccVx

vwmacc.vx vd, rs1, vs2, vm - signed widening multiply-add

Fields

§vd: VReg
§rs1: Reg
§vs2: VReg
§vm: bool
§

VwmaccsuVv

vwmaccsu.vv vd, vs1, vs2, vm - signed×unsigned widening multiply-add

Fields

§vd: VReg
§vs1: VReg
§vs2: VReg
§vm: bool
§

VwmaccsuVx

vwmaccsu.vx vd, rs1, vs2, vm - signed×unsigned widening multiply-add

Fields

§vd: VReg
§rs1: Reg
§vs2: VReg
§vm: bool
§

VwmaccusVx

vwmaccus.vx vd, rs1, vs2, vm - unsigned×signed widening multiply-add (vx only)

Fields

§vd: VReg
§rs1: Reg
§vs2: VReg
§vm: bool
§

VwadduVv

vwaddu.vv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VwadduVx

vwaddu.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VwaddVv

vwadd.vv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VwaddVx

vwadd.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VwsubuVv

vwsubu.vv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VwsubuVx

vwsubu.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VwsubVv

vwsub.vv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VwsubVx

vwsub.vx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VwadduWv

vwaddu.wv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VwadduWx

vwaddu.wx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VwaddWv

vwadd.wv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VwaddWx

vwadd.wx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VwsubuWv

vwsubu.wv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VwsubuWx

vwsubu.wx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VwsubWv

vwsub.wv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VwsubWx

vwsub.wx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VnsrlWv

vnsrl.wv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VnsrlWx

vnsrl.wx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VnsrlWi

vnsrl.wi vd, vs2, uimm, vm

Fields

§vd: VReg
§vs2: VReg
§uimm: u8
§vm: bool
§

VnsraWv

vnsra.wv vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VnsraWx

vnsra.wx vd, vs2, rs1, vm

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VnsraWi

vnsra.wi vd, vs2, uimm, vm

Fields

§vd: VReg
§vs2: VReg
§uimm: u8
§vm: bool
§

VzextVf2

vzext.vf2 vd, vs2, vm - zero-extend SEW/2 source to SEW destination

Fields

§vd: VReg
§vs2: VReg
§vm: bool
§

VzextVf4

vzext.vf4 vd, vs2, vm - zero-extend SEW/4 source to SEW destination

Fields

§vd: VReg
§vs2: VReg
§vm: bool
§

VzextVf8

vzext.vf8 vd, vs2, vm - zero-extend SEW/8 source to SEW destination

Fields

§vd: VReg
§vs2: VReg
§vm: bool
§

VsextVf2

vsext.vf2 vd, vs2, vm - sign-extend SEW/2 source to SEW destination

Fields

§vd: VReg
§vs2: VReg
§vm: bool
§

VsextVf4

vsext.vf4 vd, vs2, vm - sign-extend SEW/4 source to SEW destination

Fields

§vd: VReg
§vs2: VReg
§vm: bool
§

VsextVf8

vsext.vf8 vd, vs2, vm - sign-extend SEW/8 source to SEW destination

Fields

§vd: VReg
§vs2: VReg
§vm: bool
§

VsadduVv

vsaddu.vv vd, vs2, vs1, vm - Saturating unsigned add, vector-vector

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VsadduVx

vsaddu.vx vd, vs2, rs1, vm - Saturating unsigned add, vector-scalar

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VsadduVi

vsaddu.vi vd, vs2, imm, vm - Saturating unsigned add, vector-immediate

Fields

§vd: VReg
§vs2: VReg
§imm: i8
§vm: bool
§

VsaddVv

vsadd.vv vd, vs2, vs1, vm - Saturating signed add, vector-vector

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VsaddVx

vsadd.vx vd, vs2, rs1, vm - Saturating signed add, vector-scalar

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VsaddVi

vsadd.vi vd, vs2, imm, vm - Saturating signed add, vector-immediate

Fields

§vd: VReg
§vs2: VReg
§imm: i8
§vm: bool
§

VssubuVv

vssubu.vv vd, vs2, vs1, vm - Saturating unsigned subtract, vector-vector

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VssubuVx

vssubu.vx vd, vs2, rs1, vm - Saturating unsigned subtract, vector-scalar

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VssubVv

vssub.vv vd, vs2, vs1, vm - Saturating signed subtract, vector-vector

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VssubVx

vssub.vx vd, vs2, rs1, vm - Saturating signed subtract, vector-scalar

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VaadduVv

vaaddu.vv vd, vs2, vs1, vm - Averaging unsigned add, vector-vector

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VaadduVx

vaaddu.vx vd, vs2, rs1, vm - Averaging unsigned add, vector-scalar

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VaaddVv

vaadd.vv vd, vs2, vs1, vm - Averaging signed add, vector-vector

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VaaddVx

vaadd.vx vd, vs2, rs1, vm - Averaging signed add, vector-scalar

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VasubuVv

vasubu.vv vd, vs2, vs1, vm - Averaging unsigned subtract, vector-vector

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VasubuVx

vasubu.vx vd, vs2, rs1, vm - Averaging unsigned subtract, vector-scalar

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VasubVv

vasub.vv vd, vs2, vs1, vm - Averaging signed subtract, vector-vector

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VasubVx

vasub.vx vd, vs2, rs1, vm - Averaging signed subtract, vector-scalar

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VsmulVv

vsmul.vv vd, vs2, vs1, vm - Fractional multiply with rounding and saturation

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VsmulVx

vsmul.vx vd, vs2, rs1, vm - Fractional multiply with rounding and saturation

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VssrlVv

vssrl.vv vd, vs2, vs1, vm - Scaling shift right logical, vector-vector

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VssrlVx

vssrl.vx vd, vs2, rs1, vm - Scaling shift right logical, vector-scalar

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VssrlVi

vssrl.vi vd, vs2, imm, vm - Scaling shift right logical, vector-immediate

Fields

§vd: VReg
§vs2: VReg
§imm: u8
§vm: bool
§

VssraVv

vssra.vv vd, vs2, vs1, vm - Scaling shift right arithmetic, vector-vector

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VssraVx

vssra.vx vd, vs2, rs1, vm - Scaling shift right arithmetic, vector-scalar

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VssraVi

vssra.vi vd, vs2, imm, vm - Scaling shift right arithmetic, vector-immediate

Fields

§vd: VReg
§vs2: VReg
§imm: u8
§vm: bool
§

VnclipuWv

vnclipu.wv vd, vs2, vs1, vm - Narrowing unsigned clip, vector-vector

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VnclipuWx

vnclipu.wx vd, vs2, rs1, vm - Narrowing unsigned clip, vector-scalar

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VnclipuWi

vnclipu.wi vd, vs2, imm, vm - Narrowing unsigned clip, vector-immediate

Fields

§vd: VReg
§vs2: VReg
§imm: u8
§vm: bool
§

VnclipWv

vnclip.wv vd, vs2, vs1, vm - Narrowing signed clip, vector-vector

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VnclipWx

vnclip.wx vd, vs2, rs1, vm - Narrowing signed clip, vector-scalar

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VnclipWi

vnclip.wi vd, vs2, imm, vm - Narrowing signed clip, vector-immediate

Fields

§vd: VReg
§vs2: VReg
§imm: u8
§vm: bool
§

Vmandn

vmandn.mm vd, vs2, vs1 - vd = vs2 AND NOT vs1

funct6=011000, OPMVV, vm=1

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§

Vmand

vmand.mm vd, vs2, vs1 - vd = vs2 AND vs1

funct6=011001, OPMVV, vm=1

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§

Vmor

vmor.mm vd, vs2, vs1 - vd = vs2 OR vs1

funct6=011010, OPMVV, vm=1

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§

Vmxor

vmxor.mm vd, vs2, vs1 - vd = vs2 XOR vs1

funct6=011011, OPMVV, vm=1

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§

Vmorn

vmorn.mm vd, vs2, vs1 - vd = vs2 OR NOT vs1

funct6=011100, OPMVV, vm=1

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§

Vmnand

vmnand.mm vd, vs2, vs1 - vd = NOT(vs2 AND vs1)

funct6=011101, OPMVV, vm=1

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§

Vmnor

vmnor.mm vd, vs2, vs1 - vd = NOT(vs2 OR vs1)

funct6=011110, OPMVV, vm=1

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§

Vmxnor

vmxnor.mm vd, vs2, vs1 - vd = NOT(vs2 XOR vs1)

funct6=011111, OPMVV, vm=1

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§

Vcpop

vcpop.m rd, vs2, vm - rd = population count of mask vs2

funct6=010000, OPMVV, vs1=10000

Fields

§rd: Reg
§vs2: VReg
§vm: bool
§

Vfirst

vfirst.m rd, vs2, vm - rd = index of first set bit in mask vs2, or -1

funct6=010000, OPMVV, vs1=10001

Fields

§rd: Reg
§vs2: VReg
§vm: bool
§

Vmsbf

vmsbf.m vd, vs2, vm - set-before-first mask bit

funct6=010100, OPMVV, vs1=00001

Fields

§vd: VReg
§vs2: VReg
§vm: bool
§

Vmsof

vmsof.m vd, vs2, vm - set-only-first mask bit

funct6=010100, OPMVV, vs1=00010

Fields

§vd: VReg
§vs2: VReg
§vm: bool
§

Vmsif

vmsif.m vd, vs2, vm - set-including-first mask bit

funct6=010100, OPMVV, vs1=00011

Fields

§vd: VReg
§vs2: VReg
§vm: bool
§

Viota

viota.m vd, vs2, vm - iota: vd[i] = popcount of vs2[0..i-1]

funct6=010100, OPMVV, vs1=10000

Fields

§vd: VReg
§vs2: VReg
§vm: bool
§

Vid

vid.v vd, vm - vector element index: vd[i] = i

funct6=010100, OPMVV, vs1=10001, vs2=00000

Fields

§vd: VReg
§vm: bool
§

Vredsum

Sum reduction: vredsum.vs vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

Vredand

AND reduction: vredand.vs vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

Vredor

OR reduction: vredor.vs vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

Vredxor

XOR reduction: vredxor.vs vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

Vredminu

Unsigned minimum reduction: vredminu.vs vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

Vredmin

Signed minimum reduction: vredmin.vs vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

Vredmaxu

Unsigned maximum reduction: vredmaxu.vs vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

Vredmax

Signed maximum reduction: vredmax.vs vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

Vwredsumu

Widening unsigned sum reduction: vwredsumu.vs vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

Vwredsum

Widening signed sum reduction: vwredsum.vs vd, vs2, vs1, vm

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VmvXS

vmv.x.s rd, vs2 - Copy scalar element 0 of vs2 to GPR rd

funct6=010000, OPMVV, vs1=00000, vm=1

Fields

§rd: Reg
§vs2: VReg
§

VmvSX

vmv.s.x vd, rs1 - Copy scalar GPR rs1 to element 0 of vd

funct6=010000, OPMVX, vs2=00000, vm=1

Fields

§vd: VReg
§rs1: Reg
§

VslideupVx

vslideup.vx vd, vs2, rs1, vm - Slide elements up by scalar amount

funct6=001110, OPIVX

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VslideupVi

vslideup.vi vd, vs2, uimm, vm - Slide elements up by immediate amount

funct6=001110, OPIVI

Fields

§vd: VReg
§vs2: VReg
§uimm: u8
§vm: bool
§

VslidedownVx

vslidedown.vx vd, vs2, rs1, vm - Slide elements down by scalar amount

funct6=001111, OPIVX

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VslidedownVi

vslidedown.vi vd, vs2, uimm, vm - Slide elements down by immediate amount

funct6=001111, OPIVI

Fields

§vd: VReg
§vs2: VReg
§uimm: u8
§vm: bool
§

Vslide1upVx

vslide1up.vx vd, vs2, rs1, vm - Slide up by 1 and insert scalar at element 0

funct6=001110, OPMVX

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

Vslide1downVx

vslide1down.vx vd, vs2, rs1, vm - Slide down by 1 and insert scalar at top

funct6=001111, OPMVX

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VrgatherVv

vrgather.vv vd, vs2, vs1, vm - Gather elements from vs2 using indices in vs1

funct6=001100, OPIVV

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VrgatherVx

vrgather.vx vd, vs2, rs1, vm - Gather elements from vs2 using scalar index

funct6=001100, OPIVX

Fields

§vd: VReg
§vs2: VReg
§rs1: Reg
§vm: bool
§

VrgatherVi

vrgather.vi vd, vs2, uimm, vm - Gather elements from vs2 using immediate index

funct6=001100, OPIVI

Fields

§vd: VReg
§vs2: VReg
§uimm: u8
§vm: bool
§

Vrgatherei16Vv

vrgatherei16.vv vd, vs2, vs1, vm - Gather with 16-bit indices

funct6=001110, OPIVV

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§vm: bool
§

VcompressVm

vcompress.vm vd, vs2, vs1 - Compress active elements from vs2 under mask vs1

funct6=010111, OPMVV, vm=1 (always unmasked)

Fields

§vd: VReg
§vs2: VReg
§vs1: VReg
§

Vmv1rV

vmv1r.v vd, vs2 - Whole register move (1 register)

funct6=100111, OPIVI, simm5=00000, vm=1

Fields

§vd: VReg
§vs2: VReg
§

Vmv2rV

vmv2r.v vd, vs2 - Whole register move (2 registers)

funct6=100111, OPIVI, simm5=00001, vm=1

Fields

§vd: VReg
§vs2: VReg
§

Vmv4rV

vmv4r.v vd, vs2 - Whole register move (4 registers)

funct6=100111, OPIVI, simm5=00011, vm=1

Fields

§vd: VReg
§vs2: VReg
§

Vmv8rV

vmv8r.v vd, vs2 - Whole register move (8 registers)

funct6=100111, OPIVI, simm5=00111, vm=1

Fields

§vd: VReg
§vs2: VReg

Trait Implementations§

Source§

impl<Reg: Clone> Clone for Rv64Zve64xInstruction<Reg>

Source§

fn clone(&self) -> Rv64Zve64xInstruction<Reg>

Returns a duplicate of the value. Read more
1.0.0 · Source§

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more
Source§

impl<Reg: Debug> Debug for Rv64Zve64xInstruction<Reg>

Source§

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more
§

impl<Reg> Display for Rv64Zve64xInstruction<Reg>
where Reg: Display + Copy,

§

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more
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impl<Reg> Instruction for Rv64Zve64xInstruction<Reg>
where Reg: Register<Type = u64>,

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type Reg = Reg

A register type used by the instruction
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fn try_decode(instruction: u32) -> Option<Self>

Try to decode a single valid instruction
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fn alignment() -> u8

Instruction alignment in bytes
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fn size(&self) -> u8

Instruction size in bytes
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impl<Reg: PartialEq> PartialEq for Rv64Zve64xInstruction<Reg>

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fn eq(&self, other: &Rv64Zve64xInstruction<Reg>) -> bool

Tests for self and other values to be equal, and is used by ==.
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fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.
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impl<Reg: Copy> Copy for Rv64Zve64xInstruction<Reg>

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impl<Reg: Eq> Eq for Rv64Zve64xInstruction<Reg>

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impl<Reg> StructuralPartialEq for Rv64Zve64xInstruction<Reg>

Auto Trait Implementations§

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impl<Reg> Freeze for Rv64Zve64xInstruction<Reg>
where Reg: Freeze,

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impl<Reg> RefUnwindSafe for Rv64Zve64xInstruction<Reg>
where Reg: RefUnwindSafe,

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impl<Reg> Send for Rv64Zve64xInstruction<Reg>
where Reg: Send,

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impl<Reg> Sync for Rv64Zve64xInstruction<Reg>
where Reg: Sync,

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impl<Reg> Unpin for Rv64Zve64xInstruction<Reg>
where Reg: Unpin,

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impl<Reg> UnwindSafe for Rv64Zve64xInstruction<Reg>
where Reg: UnwindSafe,

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impl<T> Any for T
where T: 'static + ?Sized,

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fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
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impl<T> Borrow<T> for T
where T: ?Sized,

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fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
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impl<T> BorrowMut<T> for T
where T: ?Sized,

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fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
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impl<T> CloneToUninit for T
where T: Clone,

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unsafe fn clone_to_uninit(&self, dest: *mut u8)

🔬This is a nightly-only experimental API. (clone_to_uninit)
Performs copy-assignment from self to dest. Read more
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impl<T> From<T> for T

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fn from(t: T) -> T

Returns the argument unchanged.

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impl<T, U> Into<U> for T
where U: From<T>,

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fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

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impl<T> ToOwned for T
where T: Clone,

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type Owned = T

The resulting type after obtaining ownership.
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fn to_owned(&self) -> T

Creates owned data from borrowed data, usually by cloning. Read more
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fn clone_into(&self, target: &mut T)

Uses borrowed data to replace owned data, usually by cloning. Read more
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impl<T> ToString for T
where T: Display + ?Sized,

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fn to_string(&self) -> String

Converts the given value to a String. Read more
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impl<T, U> TryFrom<U> for T
where U: Into<T>,

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type Error = Infallible

The type returned in the event of a conversion error.
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fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.
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impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.
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fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.