#[repr(u8)]pub enum VReg {
Show 32 variants
V0 = 0,
V1 = 1,
V2 = 2,
V3 = 3,
V4 = 4,
V5 = 5,
V6 = 6,
V7 = 7,
V8 = 8,
V9 = 9,
V10 = 10,
V11 = 11,
V12 = 12,
V13 = 13,
V14 = 14,
V15 = 15,
V16 = 16,
V17 = 17,
V18 = 18,
V19 = 19,
V20 = 20,
V21 = 21,
V22 = 22,
V23 = 23,
V24 = 24,
V25 = 25,
V26 = 26,
V27 = 27,
V28 = 28,
V29 = 29,
V30 = 30,
V31 = 31,
}Expand description
RISC-V vector register (v0-v31)
Variants§
V0 = 0
Vector register v0 (also used as mask register)
V1 = 1
Vector register v1
V2 = 2
Vector register v2
V3 = 3
Vector register v3
V4 = 4
Vector register v4
V5 = 5
Vector register v5
V6 = 6
Vector register v6
V7 = 7
Vector register v7
V8 = 8
Vector register v8
V9 = 9
Vector register v9
V10 = 10
Vector register v10
V11 = 11
Vector register v11
V12 = 12
Vector register v12
V13 = 13
Vector register v13
V14 = 14
Vector register v14
V15 = 15
Vector register v15
V16 = 16
Vector register v16
V17 = 17
Vector register v17
V18 = 18
Vector register v18
V19 = 19
Vector register v19
V20 = 20
Vector register v20
V21 = 21
Vector register v21
V22 = 22
Vector register v22
V23 = 23
Vector register v23
V24 = 24
Vector register v24
V25 = 25
Vector register v25
V26 = 26
Vector register v26
V27 = 27
Vector register v27
V28 = 28
Vector register v28
V29 = 29
Vector register v29
V30 = 30
Vector register v30
V31 = 31
Vector register v31
Implementations§
Source§impl VReg
impl VReg
Sourcepub const fn from_bits(bits: u8) -> Option<Self>
pub const fn from_bits(bits: u8) -> Option<Self>
Create a vector register from its 5-bit encoding
Sourcepub const fn is_group_aligned(self, group: VRegGroupSize) -> bool
pub const fn is_group_aligned(self, group: VRegGroupSize) -> bool
Whether this register can be the base of a register group of group registers.
The base of a register group must be a multiple of the group size.