ab_riscv_primitives/registers/
vector.rs

1//! RISC-V vector registers
2
3use core::fmt;
4
5/// RISC-V vector register (v0-v31)
6#[derive(Clone, Copy)]
7#[derive_const(PartialEq, Eq)]
8#[repr(u8)]
9pub enum VReg {
10    /// Vector register v0 (also used as mask register)
11    V0 = 0,
12    /// Vector register v1
13    V1 = 1,
14    /// Vector register v2
15    V2 = 2,
16    /// Vector register v3
17    V3 = 3,
18    /// Vector register v4
19    V4 = 4,
20    /// Vector register v5
21    V5 = 5,
22    /// Vector register v6
23    V6 = 6,
24    /// Vector register v7
25    V7 = 7,
26    /// Vector register v8
27    V8 = 8,
28    /// Vector register v9
29    V9 = 9,
30    /// Vector register v10
31    V10 = 10,
32    /// Vector register v11
33    V11 = 11,
34    /// Vector register v12
35    V12 = 12,
36    /// Vector register v13
37    V13 = 13,
38    /// Vector register v14
39    V14 = 14,
40    /// Vector register v15
41    V15 = 15,
42    /// Vector register v16
43    V16 = 16,
44    /// Vector register v17
45    V17 = 17,
46    /// Vector register v18
47    V18 = 18,
48    /// Vector register v19
49    V19 = 19,
50    /// Vector register v20
51    V20 = 20,
52    /// Vector register v21
53    V21 = 21,
54    /// Vector register v22
55    V22 = 22,
56    /// Vector register v23
57    V23 = 23,
58    /// Vector register v24
59    V24 = 24,
60    /// Vector register v25
61    V25 = 25,
62    /// Vector register v26
63    V26 = 26,
64    /// Vector register v27
65    V27 = 27,
66    /// Vector register v28
67    V28 = 28,
68    /// Vector register v29
69    V29 = 29,
70    /// Vector register v30
71    V30 = 30,
72    /// Vector register v31
73    V31 = 31,
74}
75
76impl VReg {
77    /// Create a vector register from its 5-bit encoding
78    #[inline(always)]
79    pub const fn from_bits(bits: u8) -> Option<Self> {
80        match bits {
81            0 => Some(Self::V0),
82            1 => Some(Self::V1),
83            2 => Some(Self::V2),
84            3 => Some(Self::V3),
85            4 => Some(Self::V4),
86            5 => Some(Self::V5),
87            6 => Some(Self::V6),
88            7 => Some(Self::V7),
89            8 => Some(Self::V8),
90            9 => Some(Self::V9),
91            10 => Some(Self::V10),
92            11 => Some(Self::V11),
93            12 => Some(Self::V12),
94            13 => Some(Self::V13),
95            14 => Some(Self::V14),
96            15 => Some(Self::V15),
97            16 => Some(Self::V16),
98            17 => Some(Self::V17),
99            18 => Some(Self::V18),
100            19 => Some(Self::V19),
101            20 => Some(Self::V20),
102            21 => Some(Self::V21),
103            22 => Some(Self::V22),
104            23 => Some(Self::V23),
105            24 => Some(Self::V24),
106            25 => Some(Self::V25),
107            26 => Some(Self::V26),
108            27 => Some(Self::V27),
109            28 => Some(Self::V28),
110            29 => Some(Self::V29),
111            30 => Some(Self::V30),
112            31 => Some(Self::V31),
113            _ => None,
114        }
115    }
116
117    /// Return the 5-bit encoding of this register
118    #[inline(always)]
119    pub const fn to_bits(self) -> u8 {
120        self as u8
121    }
122}
123
124impl fmt::Display for VReg {
125    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
126        write!(f, "v{}", *self as u8)
127    }
128}
129
130impl fmt::Debug for VReg {
131    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
132        fmt::Display::fmt(self, f)
133    }
134}
135
136// TODO: CSR composition?
137/// Vector CSR addresses
138#[derive(Debug, Clone, Copy)]
139#[derive_const(PartialEq, Eq)]
140pub enum VectorCsr {
141    /// Vector start element index (URW)
142    Vstart,
143    /// Fixed-point saturation flag (URW)
144    Vxsat,
145    /// Fixed-point rounding mode (URW)
146    Vxrm,
147    /// Vector control and status register (URW)
148    Vcsr,
149    /// Vector length (URO)
150    Vl,
151    /// Vector data type register (URO)
152    Vtype,
153    /// VLEN/8 (vector register length in bytes) (URO)
154    Vlenb,
155}
156
157impl VectorCsr {
158    /// Try to match a CSR index to a vector CSR
159    #[inline(always)]
160    pub const fn from_csr_index(index: u16) -> Option<Self> {
161        match index {
162            0x008 => Some(Self::Vstart),
163            0x009 => Some(Self::Vxsat),
164            0x00A => Some(Self::Vxrm),
165            0x00F => Some(Self::Vcsr),
166            0xC20 => Some(Self::Vl),
167            0xC21 => Some(Self::Vtype),
168            0xC22 => Some(Self::Vlenb),
169            _ => None,
170        }
171    }
172
173    /// Convert vector CSR to its corresponding CSR index
174    #[inline(always)]
175    pub const fn to_csr_index(self) -> u16 {
176        match self {
177            Self::Vstart => 0x008,
178            Self::Vxsat => 0x009,
179            Self::Vxrm => 0x00A,
180            Self::Vcsr => 0x00F,
181            Self::Vl => 0xC20,
182            Self::Vtype => 0xC21,
183            Self::Vlenb => 0xC22,
184        }
185    }
186}
ab_riscv_primitives/registers/vector.rs

ab_riscv_primitives/registers/
vector.rs
