ab_riscv_primitives/registers/
vector.rs

1//! RISC-V vector registers
2
3use core::fmt;
4
5/// RISC-V vector register (v0-v31)
6#[derive(Clone, Copy, PartialEq, Eq)]
7#[repr(u8)]
8pub enum VReg {
9    /// Vector register v0 (also used as mask register)
10    V0 = 0,
11    /// Vector register v1
12    V1 = 1,
13    /// Vector register v2
14    V2 = 2,
15    /// Vector register v3
16    V3 = 3,
17    /// Vector register v4
18    V4 = 4,
19    /// Vector register v5
20    V5 = 5,
21    /// Vector register v6
22    V6 = 6,
23    /// Vector register v7
24    V7 = 7,
25    /// Vector register v8
26    V8 = 8,
27    /// Vector register v9
28    V9 = 9,
29    /// Vector register v10
30    V10 = 10,
31    /// Vector register v11
32    V11 = 11,
33    /// Vector register v12
34    V12 = 12,
35    /// Vector register v13
36    V13 = 13,
37    /// Vector register v14
38    V14 = 14,
39    /// Vector register v15
40    V15 = 15,
41    /// Vector register v16
42    V16 = 16,
43    /// Vector register v17
44    V17 = 17,
45    /// Vector register v18
46    V18 = 18,
47    /// Vector register v19
48    V19 = 19,
49    /// Vector register v20
50    V20 = 20,
51    /// Vector register v21
52    V21 = 21,
53    /// Vector register v22
54    V22 = 22,
55    /// Vector register v23
56    V23 = 23,
57    /// Vector register v24
58    V24 = 24,
59    /// Vector register v25
60    V25 = 25,
61    /// Vector register v26
62    V26 = 26,
63    /// Vector register v27
64    V27 = 27,
65    /// Vector register v28
66    V28 = 28,
67    /// Vector register v29
68    V29 = 29,
69    /// Vector register v30
70    V30 = 30,
71    /// Vector register v31
72    V31 = 31,
73}
74
75impl VReg {
76    /// Create a vector register from its 5-bit encoding
77    #[inline(always)]
78    pub const fn from_bits(bits: u8) -> Option<Self> {
79        match bits {
80            0 => Some(Self::V0),
81            1 => Some(Self::V1),
82            2 => Some(Self::V2),
83            3 => Some(Self::V3),
84            4 => Some(Self::V4),
85            5 => Some(Self::V5),
86            6 => Some(Self::V6),
87            7 => Some(Self::V7),
88            8 => Some(Self::V8),
89            9 => Some(Self::V9),
90            10 => Some(Self::V10),
91            11 => Some(Self::V11),
92            12 => Some(Self::V12),
93            13 => Some(Self::V13),
94            14 => Some(Self::V14),
95            15 => Some(Self::V15),
96            16 => Some(Self::V16),
97            17 => Some(Self::V17),
98            18 => Some(Self::V18),
99            19 => Some(Self::V19),
100            20 => Some(Self::V20),
101            21 => Some(Self::V21),
102            22 => Some(Self::V22),
103            23 => Some(Self::V23),
104            24 => Some(Self::V24),
105            25 => Some(Self::V25),
106            26 => Some(Self::V26),
107            27 => Some(Self::V27),
108            28 => Some(Self::V28),
109            29 => Some(Self::V29),
110            30 => Some(Self::V30),
111            31 => Some(Self::V31),
112            _ => None,
113        }
114    }
115
116    /// Return the 5-bit encoding of this register
117    #[inline(always)]
118    pub const fn bits(self) -> u8 {
119        self as u8
120    }
121}
122
123impl fmt::Display for VReg {
124    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
125        write!(f, "v{}", *self as u8)
126    }
127}
128
129impl fmt::Debug for VReg {
130    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
131        fmt::Display::fmt(self, f)
132    }
133}
134
135// TODO: CSR composition?
136/// Vector CSR addresses
137#[derive(Debug, Clone, Copy, PartialEq, Eq)]
138#[repr(u16)]
139pub enum VCsr {
140    /// Vector start element index (URW)
141    Vstart = 0x008,
142    /// Fixed-point saturation flag (URW)
143    Vxsat = 0x009,
144    /// Fixed-point rounding mode (URW)
145    Vxrm = 0x00A,
146    /// Vector control and status register (URW)
147    Vcsr = 0x00F,
148    /// Vector length (URO)
149    Vl = 0xC20,
150    /// Vector data type register (URO)
151    Vtype = 0xC21,
152    /// VLEN/8 (vector register length in bytes) (URO)
153    Vlenb = 0xC22,
154}
155
156impl VCsr {
157    /// Try to match a CSR index to a vector CSR
158    #[inline(always)]
159    pub const fn from_index(index: u16) -> Option<Self> {
160        match index {
161            0x008 => Some(Self::Vstart),
162            0x009 => Some(Self::Vxsat),
163            0x00A => Some(Self::Vxrm),
164            0x00F => Some(Self::Vcsr),
165            0xC20 => Some(Self::Vl),
166            0xC21 => Some(Self::Vtype),
167            0xC22 => Some(Self::Vlenb),
168            _ => None,
169        }
170    }
171}
ab_riscv_primitives/registers/vector.rs

ab_riscv_primitives/registers/
vector.rs
