#[repr(u16)]pub enum MCsr {
Show 24 variants
Mvendorid = 3_857,
Marchid = 3_858,
Mimpid = 3_859,
Mhartid = 3_860,
Mconfigptr = 3_861,
Mstatus = 768,
Misa = 769,
Mie = 772,
Mtvec = 773,
Menvcfg = 778,
Mstatush = 784,
Menvcfgh = 794,
Mcountinhibit = 800,
Mseccfg = 1_863,
Mseccfgh = 1_879,
Mscratch = 832,
Mepc = 833,
Mcause = 834,
Mtval = 835,
Mip = 836,
Mcycle = 2_816,
Minstret = 2_818,
Mcycleh = 2_944,
Minstreth = 2_946,
}Expand description
Machine CSR addresses (core mandatory registers from the Privileged Spec)
Variants§
Mvendorid = 3_857
Machine vendor ID register (MRO)
Marchid = 3_858
Machine architecture ID register (MRO)
Mimpid = 3_859
Machine implementation ID register (MRO)
Mhartid = 3_860
Hart ID register (MRO)
Mconfigptr = 3_861
Pointer to the configuration data structure (MRO)
Mstatus = 768
Machine status register (MRW)
Misa = 769
Machine ISA and extensions register (MRW)
Mie = 772
Machine interrupt-enable register (MRW)
Mtvec = 773
Machine trap-vector base address register (MRW)
Menvcfg = 778
Machine environment configuration register (MRW)
Mstatush = 784
Additional machine status register, RV32 only (MRW)
Menvcfgh = 794
Upper 32 bits of menvcfg, RV32 only (MRW)
Mcountinhibit = 800
Machine count-inhibit register (MRW)
Mseccfg = 1_863
Machine security configuration register (MRW)
Mseccfgh = 1_879
Upper 32 bits of mseccfg, RV32 only (MRW)
Mscratch = 832
Machine scratch register (MRW)
Mepc = 833
Machine exception program counter (MRW)
Mcause = 834
Machine trap cause (MRW)
Mtval = 835
Machine trap value (MRW)
Mip = 836
Machine interrupt pending (MRW)
Mcycle = 2_816
Machine cycle counter (MRW)
Minstret = 2_818
Machine instructions-retired counter (MRW)
Mcycleh = 2_944
Upper 32 bits of mcycle, RV32 only (MRW)
Minstreth = 2_946
Upper 32 bits of minstret, RV32 only (MRW)