Skip to main content

Module machine

ab_riscv_primitives::registers

Module machine

Expand description

Machine-mode registers

Enums§

MCause: Combined mcause CSR value
MCauseException: Machine exception causes (mcause[XLEN‑1] = 0)
MCauseInterrupt: Machine interrupt causes (mcause[XLEN‑1] = 1)
MCsr: Machine CSR addresses (core mandatory registers from the Privileged Spec)