pub struct Vtype<Hart>where
Hart: VectorHartConfig,{ /* private fields */ }Expand description
Decoded vtype register contents.
The vtype CSR controls the interpretation of the vector register file: element width, register grouping, and tail/mask agnostic policies.
The raw encoding is XLEN-dependent (vill is at bit XLEN-1), but this decoded form is XLEN-independent.
Implementations§
Source§impl<Hart> Vtype<Hart>where
Hart: VectorHartConfig,
impl<Hart> Vtype<Hart>where
Hart: VectorHartConfig,
Sourcepub const fn eew_register_count(&self, eew: Eew) -> Option<VRegGroupSize>
pub const fn eew_register_count(&self, eew: Eew) -> Option<VRegGroupSize>
Number of registers in a group of elements with effective element width eew, where
EMUL = (EEW / SEW) * LMUL.
Returns None when EEW exceeds ELEN or EMUL falls outside the legal range
[1/8, 8], both of which are reserved.
Sourcepub const fn vlmax(&self) -> Vl
pub const fn vlmax(&self) -> Vl
VLMAX = LMUL * VLEN / SEW, which is at least 1 for any valid vtype
Sourcepub const fn from_raw<Reg>(raw: Reg::Type) -> Option<Self>where
Reg: Register,
pub const fn from_raw<Reg>(raw: Reg::Type) -> Option<Self>where
Reg: Register,
Decode from raw register value.
The XLEN is taken from Reg::XLEN and must be 32 for RV32 or 64 for RV64. The vill bit
is placed at bit position Reg::XLEN - 1.
All bits in [Reg::XLEN-1:8] must be zero; non-zero bits indicate an unrecognized
encoding and cause None to be returned (this includes vill).
Sourcepub const fn to_raw<Reg>(self) -> Reg::Typewhere
Reg: Register,
pub const fn to_raw<Reg>(self) -> Reg::Typewhere
Reg: Register,
Encode to a raw vtype register value of type Reg::Type.
The encoded value contains vlmul, vsew, vta, and vma in bits [7:0] with
vill = 0. To construct a raw value with vill = 1 (illegal configuration), use
Self::illegal_raw.
Sourcepub const fn illegal_raw<Reg>() -> Reg::Typewhere
Reg: Register,
pub const fn illegal_raw<Reg>() -> Reg::Typewhere
Reg: Register,
Construct a raw value for vtype with vill=1 (illegal configuration).
Per spec: when vill is set, the remaining bits are zero and vl is also set to zero. Any
subsequent vector instruction that depends on vtype will raise an illegal-instruction
exception.