pub enum Rv64ZcmpInstruction<Hart>where
Hart: HartConfig,{
Show 40 variants
CAddi4spn {
rd: Hart::Reg,
nzuimm: u16,
/* private fields */
},
CLw {
rs1: Hart::Reg,
rd: Hart::Reg,
uimm: u8,
/* private fields */
},
CLd {
rs1: Hart::Reg,
rd: Hart::Reg,
uimm: u8,
/* private fields */
},
CSw {
rs1: Hart::Reg,
rs2: Hart::Reg,
uimm: u8,
},
CSd {
rs1: Hart::Reg,
rs2: Hart::Reg,
uimm: u8,
},
CNop { /* private fields */ },
CAddi {
rd: Hart::Reg,
nzimm: i8,
/* private fields */
},
CAddiw {
rd: Hart::Reg,
imm: i8,
/* private fields */
},
CLi {
rd: Hart::Reg,
imm: i8,
/* private fields */
},
CAddi16sp {
nzimm: i16,
/* private fields */
},
CLui {
rd: Hart::Reg,
nzimm: I24,
/* private fields */
},
CSrli {
rd: Hart::Reg,
shamt: Shamt<u64>,
/* private fields */
},
CSrai {
rd: Hart::Reg,
shamt: Shamt<u64>,
/* private fields */
},
CAndi {
rd: Hart::Reg,
imm: i8,
/* private fields */
},
CSub {
rs2: Hart::Reg,
rd: Hart::Reg,
/* private fields */
},
CXor {
rs2: Hart::Reg,
rd: Hart::Reg,
/* private fields */
},
COr {
rs2: Hart::Reg,
rd: Hart::Reg,
/* private fields */
},
CAnd {
rs2: Hart::Reg,
rd: Hart::Reg,
/* private fields */
},
CSubw {
rs2: Hart::Reg,
rd: Hart::Reg,
/* private fields */
},
CAddw {
rs2: Hart::Reg,
rd: Hart::Reg,
/* private fields */
},
CJ {
imm: i16,
/* private fields */
},
CBeqz {
rs1: Hart::Reg,
imm: i16,
/* private fields */
},
CBnez {
rs1: Hart::Reg,
imm: i16,
/* private fields */
},
CSlli {
rd: Hart::Reg,
shamt: Shamt<u64>,
/* private fields */
},
CLwsp {
rd: Hart::Reg,
uimm: u8,
/* private fields */
},
CLdsp {
rd: Hart::Reg,
uimm: u16,
/* private fields */
},
CJr {
rs1: Hart::Reg,
/* private fields */
},
CMv {
rs2: Hart::Reg,
rd: Hart::Reg,
/* private fields */
},
CEbreak { /* private fields */ },
CJalr {
rs1: Hart::Reg,
/* private fields */
},
CAdd {
rs2: Hart::Reg,
rd: Hart::Reg,
/* private fields */
},
CSwsp {
rs2: Hart::Reg,
uimm: u8,
/* private fields */
},
CSdsp {
rs2: Hart::Reg,
uimm: u16,
/* private fields */
},
CUnimp { /* private fields */ },
CmPush {
urlist: ZcmpUrlist<Hart::Reg>,
stack_adj: u8,
/* private fields */
},
CmPop {
urlist: ZcmpUrlist<Hart::Reg>,
stack_adj: u8,
/* private fields */
},
CmPopretz {
urlist: ZcmpUrlist<Hart::Reg>,
stack_adj: u8,
/* private fields */
},
CmPopret {
urlist: ZcmpUrlist<Hart::Reg>,
stack_adj: u8,
/* private fields */
},
CmMva01s {
rs1: Hart::Reg,
rs2: Hart::Reg,
},
CmMvsa01 {
rs1: Hart::Reg,
rs2: Hart::Reg,
},
}Expand description
Zcmp compressed instruction set
Variants§
CAddi4spn
C.ADDI4SPN rd’ = sp + nzuimm (nzuimm ∈ 4..1020 step 4)
CLw
C.LW rd’ = sext(mem32[rs1’ + uimm])
CLd
C.LD rd’ = mem64[rs1’ + uimm]
CSw
C.SW mem32[rs1’ + uimm] = rs2’
CSd
C.SD mem64[rs1’ + uimm] = rs2’
CNop
C.NOP (ADDI x0, x0, 0 with rd==x0 and nzimm==0)
CAddi
C.ADDI rd += nzimm (rd != x0)
CAddiw
C.ADDIW rd = sext((rd[31:0] + imm)[31:0]) (rd != x0)
CLi
C.LI rd = sext(imm) (rd=x0 is a HINT)
CAddi16sp
C.ADDI16SP sp += nzimm*16 (nzimm != 0)
CLui
C.LUI rd = sext(nzimm << 12) (rd != x0, rd != x2, nzimm != 0)
CSrli
C.SRLI rd’ >>= shamt (logical right shift; shamt=0 with rd’=x0 is a HINT)
CSrai
C.SRAI rd’ >>= shamt (arithmetic right shift; shamt=0 with rd’=x0 is a HINT)
CAndi
C.ANDI rd’ &= sext(imm)
CSub
C.SUB rd’ -= rs2’
CXor
C.XOR rd’ ^= rs2’
COr
C.OR rd’ |= rs2’
CAnd
C.AND rd’ &= rs2’
CSubw
C.SUBW rd’ = sext((rd’[31:0] - rs2’[31:0])[31:0])
CAddw
C.ADDW rd’ = sext((rd’[31:0] + rs2’[31:0])[31:0])
CJ
C.J pc += sext(imm)
CBeqz
C.BEQZ if rs1’ == 0: pc += sext(imm)
CBnez
C.BNEZ if rs1’ != 0: pc += sext(imm)
CSlli
C.SLLI rd <<= shamt (rd=x0 or shamt=0 is a HINT)
CLwsp
C.LWSP rd = sext(mem32[sp + uimm]) (rd != x0)
CLdsp
C.LDSP rd = mem64[sp + uimm] (rd != x0)
CJr
C.JR pc = rs1 (rs1 != x0)
CMv
C.MV rd = rs2 (rs2 != x0; rd=x0 is a HINT)
CEbreak
C.EBREAK
CJalr
C.JALR ra = pc+2; pc = rs1 (rs1 != x0)
CAdd
C.ADD rd += rs2 (rs2 != x0; rd=x0 is a HINT)
CSwsp
C.SWSP mem32[sp + uimm] = rs2
CSdsp
C.SDSP mem64[sp + uimm] = rs2
CUnimp
CmPush
CM.PUSH - push reg_list, decrement sp by stack_adj
stack_adj = urlist.stack_adj_base() + spimm * 16 from the encoding.
CmPop
CM.POP - pop reg_list, increment sp by stack_adj (no return)
CmPopretz
CM.POPRETZ - pop reg_list, set a0=0, increment sp, return
CmPopret
CM.POPRET - pop reg_list, increment sp, return
CmMva01s
CM.MVA01S - a0 = r1s’, a1 = r2s’.
The fields are called both r1s/r2s and rs1/rs2 in the spec, rs1/rs2 is used here for consistency with other instructions.
CmMvsa01
CM.MVSA01 - r1s’ = a0, r2s’ = a1 (r1s’ != r2s’).
The fields are called both r1s/r2s and rs1/rs2 in the spec, rs1/rs2 is used here for consistency with other instructions.
Trait Implementations§
Source§impl<Hart> Clone for Rv64ZcmpInstruction<Hart>
impl<Hart> Clone for Rv64ZcmpInstruction<Hart>
Source§fn clone(&self) -> Rv64ZcmpInstruction<Hart>
fn clone(&self) -> Rv64ZcmpInstruction<Hart>
1.0.0 (const: unstable) · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read moreimpl<Hart> Copy for Rv64ZcmpInstruction<Hart>
Source§impl<Hart> Debug for Rv64ZcmpInstruction<Hart>
impl<Hart> Debug for Rv64ZcmpInstruction<Hart>
§impl<Reg, Hart> Display for Rv64ZcmpInstruction<Hart>where
Reg: Register,
Hart: HartConfig<Reg = Reg>,
impl<Reg, Hart> Display for Rv64ZcmpInstruction<Hart>where
Reg: Register,
Hart: HartConfig<Reg = Reg>,
impl<Hart> Eq for Rv64ZcmpInstruction<Hart>
§impl<Reg, Hart> Instruction for Rv64ZcmpInstruction<Hart>
impl<Reg, Hart> Instruction for Rv64ZcmpInstruction<Hart>
§const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]
§const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
const OWN_ISA_EXTENSIONS: &'static [IsaExtension]
§fn try_decode(instruction: u32) -> Option<Self>
fn try_decode(instruction: u32) -> Option<Self>
Source§const ISA_STRING: &'static str = _
const ISA_STRING: &'static str = _
Tag_RISCV_arch attribute of ELF files, for example,
rv64i2p1_m2p0_zmmul1p0. Read moreSource§fn implements_extension<E>() -> boolwhere
E: Instruction<Hart = Self::Hart>,
fn implements_extension<E>() -> boolwhere
E: Instruction<Hart = Self::Hart>,
Self::IMPLEMENTED_EXTENSIONS for details