Enum Rv64ZcbInstruction 

pub enum Rv64ZcbInstruction<Reg> {
    CLbu {
        rd: Reg,
        rs1: Reg,
        uimm: u8,
    },
    CLh {
        rd: Reg,
        rs1: Reg,
        uimm: u8,
    },
    CLhu {
        rd: Reg,
        rs1: Reg,
        uimm: u8,
    },
    CSb {
        rs1: Reg,
        rs2: Reg,
        uimm: u8,
    },
    CSh {
        rs1: Reg,
        rs2: Reg,
        uimm: u8,
    },
    CZextB {
        rd: Reg,
    },
    CSextB {
        rd: Reg,
    },
    CZextH {
        rd: Reg,
    },
    CSextH {
        rd: Reg,
    },
    CZextW {
        rd: Reg,
    },
    CNot {
        rd: Reg,
    },
    CMul {
        rd: Reg,
        rs2: Reg,
    },
}

RISC-V RV64 Zcb compressed instruction set.

All register operands are prime-field (x8–x15) registers.

Variants

CLbu

C.LBU rd’ = zero_extend(mem8[rs1’ + uimm]) uimm ∈ {0,1,2,3}

Fields

rd: Reg

rs1: Reg

uimm: u8

CLh

C.LH rd’ = sign_extend(mem16[rs1’ + uimm]) uimm ∈ {0,2}

Fields

rd: Reg

rs1: Reg

uimm: u8

CLhu

C.LHU rd’ = zero_extend(mem16[rs1’ + uimm]) uimm ∈ {0,2}

Fields

rd: Reg

rs1: Reg

uimm: u8

CSb

C.SB mem8[rs1’ + uimm] = rs2’ uimm ∈ {0,1,2,3}

Fields

rs1: Reg

rs2: Reg

uimm: u8

CSh

C.SH mem16[rs1’ + uimm] = rs2’ uimm ∈ {0,2}

Fields

rs1: Reg

rs2: Reg

uimm: u8

CZextB

C.ZEXT.B rd’ = rd’ & 0xff

Fields

rd: Reg

CSextB

C.SEXT.B rd’ = sext(rd’[7:0]) (requires Zbb)

Fields

rd: Reg

CZextH

C.ZEXT.H rd’ = rd’ & 0xffff (requires Zbb)

Fields

rd: Reg

CSextH

C.SEXT.H rd’ = sext(rd’[15:0]) (requires Zbb)

Fields

rd: Reg

CZextW

C.ZEXT.W rd’ = rd’ & 0xffff_ffff (requires Zba)

Fields

rd: Reg

CNot

C.NOT rd’ = ~rd’

Fields

rd: Reg

CMul

C.MUL rd’ = (rd’ * rs2’)[XLEN-1:0] (requires M or Zmmul)

Fields

rd: Reg

rs2: Reg

Trait Implementations

impl<Reg: Clone> Clone for Rv64ZcbInstruction<Reg>

fn clone(&self) -> Rv64ZcbInstruction<Reg>

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<Reg: Debug> Debug for Rv64ZcbInstruction<Reg>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<Reg> Display for Rv64ZcbInstruction<Reg>

where Reg: Display,

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<Reg> Instruction for Rv64ZcbInstruction<Reg>

where Reg: Register<Type = u64>,

type Reg = Reg

A register type used by the instruction

fn try_decode(instruction: u32) -> Option<Self>

Try to decode a single valid instruction

fn alignment() -> u8

Instruction alignment in bytes

fn size(&self) -> u8

Instruction size in bytes

impl<Reg: PartialEq> PartialEq for Rv64ZcbInstruction<Reg>

fn eq(&self, other: &Rv64ZcbInstruction<Reg>) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl<Reg: Copy> Copy for Rv64ZcbInstruction<Reg>

impl<Reg: Eq> Eq for Rv64ZcbInstruction<Reg>

impl<Reg> StructuralPartialEq for Rv64ZcbInstruction<Reg>