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Rv64ZcaInstruction

ab_riscv_primitives::instructions::rv64::c::zca

Enum Rv64ZcaInstruction

pub enum Rv64ZcaInstruction<Reg> {
Show 34 variants    CAddi4spn {
        rd: Reg,
        nzuimm: u16,
    },
    CLw {
        rd: Reg,
        rs1: Reg,
        uimm: u8,
    },
    CLd {
        rd: Reg,
        rs1: Reg,
        uimm: u8,
    },
    CSw {
        rs1: Reg,
        rs2: Reg,
        uimm: u8,
    },
    CSd {
        rs1: Reg,
        rs2: Reg,
        uimm: u8,
    },
    CNop,
    CAddi {
        rd: Reg,
        nzimm: i8,
    },
    CAddiw {
        rd: Reg,
        imm: i8,
    },
    CLi {
        rd: Reg,
        imm: i8,
    },
    CAddi16sp {
        nzimm: i16,
    },
    CLui {
        rd: Reg,
        nzimm: i32,
    },
    CSrli {
        rd: Reg,
        shamt: u8,
    },
    CSrai {
        rd: Reg,
        shamt: u8,
    },
    CAndi {
        rd: Reg,
        imm: i8,
    },
    CSub {
        rd: Reg,
        rs2: Reg,
    },
    CXor {
        rd: Reg,
        rs2: Reg,
    },
    COr {
        rd: Reg,
        rs2: Reg,
    },
    CAnd {
        rd: Reg,
        rs2: Reg,
    },
    CSubw {
        rd: Reg,
        rs2: Reg,
    },
    CAddw {
        rd: Reg,
        rs2: Reg,
    },
    CJ {
        imm: i16,
    },
    CBeqz {
        rs1: Reg,
        imm: i16,
    },
    CBnez {
        rs1: Reg,
        imm: i16,
    },
    CSlli {
        rd: Reg,
        shamt: u8,
    },
    CLwsp {
        rd: Reg,
        uimm: u8,
    },
    CLdsp {
        rd: Reg,
        uimm: u16,
    },
    CJr {
        rs1: Reg,
    },
    CMv {
        rd: Reg,
        rs2: Reg,
    },
    CEbreak,
    CJalr {
        rs1: Reg,
    },
    CAdd {
        rd: Reg,
        rs2: Reg,
    },
    CSwsp {
        rs2: Reg,
        uimm: u8,
    },
    CSdsp {
        rs2: Reg,
        uimm: u16,
    },
    CUnimp,
}

Expand description

RISC-V RV64 Zca compressed instruction set

Variants§

CAddi4spn

C.ADDI4SPN rd’ = sp + nzuimm (nzuimm ∈ 4..1020 step 4)

Fields

§rd: Reg

§nzuimm: u16

CLw

C.LW rd’ = sext(mem32[rs1’ + uimm])

Fields

§rd: Reg

§rs1: Reg

§uimm: u8

CLd

C.LD rd’ = mem64[rs1’ + uimm]

Fields

§rd: Reg

§rs1: Reg

§uimm: u8

CSw

C.SW mem32[rs1’ + uimm] = rs2’

Fields

§rs1: Reg

§rs2: Reg

§uimm: u8

CSd

C.SD mem64[rs1’ + uimm] = rs2’

Fields

§rs1: Reg

§rs2: Reg

§uimm: u8

CNop

C.NOP (ADDI x0, x0, 0 with rd==x0 and nzimm==0)

CAddi

C.ADDI rd += nzimm (rd != x0)

Fields

§rd: Reg

§nzimm: i8

CAddiw

C.ADDIW rd = sext((rd[31:0] + imm)[31:0]) (rd != x0)

Fields

§rd: Reg

§imm: i8

CLi

C.LI rd = sext(imm) (rd=x0 is a HINT)

Fields

§rd: Reg

§imm: i8

CAddi16sp

C.ADDI16SP sp += nzimm*16 (nzimm != 0)

Fields

§nzimm: i16

CLui

C.LUI rd = sext(nzimm << 12) (rd != x0, rd != x2, nzimm != 0)

Fields

§rd: Reg

§nzimm: i32

CSrli

C.SRLI rd’ >>= shamt (logical right shift; shamt=0 with rd’=x0 is a HINT)

Fields

§rd: Reg

§shamt: u8

CSrai

C.SRAI rd’ >>= shamt (arithmetic right shift; shamt=0 with rd’=x0 is a HINT)

Fields

§rd: Reg

§shamt: u8

CAndi

C.ANDI rd’ &= sext(imm)

Fields

§rd: Reg

§imm: i8

CSub

C.SUB rd’ -= rs2’

Fields

§rd: Reg

§rs2: Reg

CXor

C.XOR rd’ ^= rs2’

Fields

§rd: Reg

§rs2: Reg

COr

C.OR rd’ |= rs2’

Fields

§rd: Reg

§rs2: Reg

CAnd

C.AND rd’ &= rs2’

Fields

§rd: Reg

§rs2: Reg

CSubw

C.SUBW rd’ = sext((rd’[31:0] - rs2’[31:0])[31:0])

Fields

§rd: Reg

§rs2: Reg

CAddw

C.ADDW rd’ = sext((rd’[31:0] + rs2’[31:0])[31:0])

Fields

§rd: Reg

§rs2: Reg

CJ

C.J pc += sext(imm)

Fields

§imm: i16

CBeqz

C.BEQZ if rs1’ == 0: pc += sext(imm)

Fields

§rs1: Reg

§imm: i16

CBnez

C.BNEZ if rs1’ != 0: pc += sext(imm)

Fields

§rs1: Reg

§imm: i16

CSlli

C.SLLI rd <<= shamt (rd=x0 or shamt=0 is a HINT)

Fields

§rd: Reg

§shamt: u8

CLwsp

C.LWSP rd = sext(mem32[sp + uimm]) (rd != x0)

Fields

§rd: Reg

§uimm: u8

CLdsp

C.LDSP rd = mem64[sp + uimm] (rd != x0)

Fields

§rd: Reg

§uimm: u16

CJr

C.JR pc = rs1 (rs1 != x0)

Fields

§rs1: Reg

CMv

C.MV rd = rs2 (rs2 != x0; rd=x0 is a HINT)

Fields

§rd: Reg

§rs2: Reg

CEbreak

C.EBREAK

CJalr

C.JALR ra = pc+2; pc = rs1 (rs1 != x0)

Fields

§rs1: Reg

CAdd

C.ADD rd += rs2 (rs2 != x0; rd=x0 is a HINT)

Fields

§rd: Reg

§rs2: Reg

CSwsp

C.SWSP mem32[sp + uimm] = rs2

Fields

§rs2: Reg

§uimm: u8

CSdsp

C.SDSP mem64[sp + uimm] = rs2

Fields

§rs2: Reg

§uimm: u16

CUnimp

Trait Implementations§

impl<Reg: Clone> Clone for Rv64ZcaInstruction<Reg>

fn clone(&self) -> Rv64ZcaInstruction<Reg>

Returns a duplicate of the value. Read more

1.0.0 · Source§

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more

impl<Reg: Debug> Debug for Rv64ZcaInstruction<Reg>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more

impl<Reg> Display for Rv64ZcaInstruction<Reg>
where Reg: Display,

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more

impl<Reg> Instruction for Rv64ZcaInstruction<Reg>
where Reg: Register<Type = u64>,

type Reg = Reg

A register type used by the instruction

fn try_decode(instruction: u32) -> Option<Self>

Try to decode a single valid instruction

fn alignment() -> u8

Instruction alignment in bytes

fn size(&self) -> u8

Instruction size in bytes

impl<Reg: PartialEq> PartialEq for Rv64ZcaInstruction<Reg>

fn eq(&self, other: &Rv64ZcaInstruction<Reg>) -> bool

Tests for self and other values to be equal, and is used by ==.

1.0.0 · Source§

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl<Reg: Copy> Copy for Rv64ZcaInstruction<Reg>

impl<Reg: Eq> Eq for Rv64ZcaInstruction<Reg>

impl<Reg> StructuralPartialEq for Rv64ZcaInstruction<Reg>

Auto Trait Implementations§

impl<Reg> Freeze for Rv64ZcaInstruction<Reg>
where Reg: Freeze,

impl<Reg> RefUnwindSafe for Rv64ZcaInstruction<Reg>
where Reg: RefUnwindSafe,

impl<Reg> Send for Rv64ZcaInstruction<Reg>
where Reg: Send,

impl<Reg> Sync for Rv64ZcaInstruction<Reg>
where Reg: Sync,

impl<Reg> Unpin for Rv64ZcaInstruction<Reg>
where Reg: Unpin,

impl<Reg> UnsafeUnpin for Rv64ZcaInstruction<Reg>
where Reg: UnsafeUnpin,

impl<Reg> UnwindSafe for Rv64ZcaInstruction<Reg>
where Reg: UnwindSafe,

Blanket Implementations§

impl<T> Any for T
where T: 'static + ?Sized,

fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more

impl<T> Borrow<T> for T
where T: ?Sized,

fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more

impl<T> BorrowMut<T> for T
where T: ?Sized,

fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more

impl<T> CloneToUninit for T
where T: Clone,

unsafe fn clone_to_uninit(&self, dest: *mut u8)

🔬This is a nightly-only experimental API. (clone_to_uninit)

Performs copy-assignment from self to dest. Read more

impl<T> From<T> for T

fn from(t: T) -> T

Returns the argument unchanged.

impl<T, U> Into<U> for T
where U: From<T>,

fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

impl<T> ToOwned for T
where T: Clone,

type Owned = T

The resulting type after obtaining ownership.

fn to_owned(&self) -> T

Creates owned data from borrowed data, usually by cloning. Read more

fn clone_into(&self, target: &mut T)

Uses borrowed data to replace owned data, usually by cloning. Read more

impl<T> ToString for T
where T: Display + ?Sized,

fn to_string(&self) -> String

Converts the given value to a String. Read more

impl<T, U> TryFrom<U> for T
where U: Into<T>,

type Error = Infallible

The type returned in the event of a conversion error.

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.

impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.