Enum Rv32ZknhInstruction 

pub enum Rv32ZknhInstruction<Reg> {
    Sha256Sig0 {
        rd: Reg,
        rs1: Reg,
    },
    Sha256Sig1 {
        rd: Reg,
        rs1: Reg,
    },
    Sha256Sum0 {
        rd: Reg,
        rs1: Reg,
    },
    Sha256Sum1 {
        rd: Reg,
        rs1: Reg,
    },
    Sha512Sig0h {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sha512Sig0l {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sha512Sig1h {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sha512Sig1l {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sha512Sum0r {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sha512Sum1r {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
}

RISC-V RV32 Zknh instruction (SHA-256 and SHA-512 sigma/sum functions).

SHA-256 instructions take a single source register. SHA-512 instructions take two source registers because 64-bit operands must be split across two 32-bit registers on RV32. The register conventions differ by instruction and follow the RISC-V scalar crypto Sail model exactly:

• sha512sig0l, sha512sig1l: rs1 = LOW word, rs2 = HIGH word
• sha512sig0h, sha512sig1h: rs1 = HIGH word, rs2 = LOW word
• sha512sum0r, sha512sum1r: rs1 = LOW word, rs2 = HIGH word

For sha512sum0r and sha512sum1r the Sail pseudocode builds the 64-bit operand as x[63:32] = X(rs2), x[31:0] = X(rs1) (rs2 is the HIGH half) and writes the low 32 bits of the result to rd.

Variants

Sha256Sig0

Fields

rd: Reg

rs1: Reg

Sha256Sig1

Fields

rd: Reg

rs1: Reg

Sha256Sum0

Fields

rd: Reg

rs1: Reg

Sha256Sum1

Fields

rd: Reg

rs1: Reg

Sha512Sig0h

Fields

rd: Reg

rs1: Reg

rs2: Reg

Sha512Sig0l

Fields

rd: Reg

rs1: Reg

rs2: Reg

Sha512Sig1h

Fields

rd: Reg

rs1: Reg

rs2: Reg

Sha512Sig1l

Fields

rd: Reg

rs1: Reg

rs2: Reg

Sha512Sum0r

Fields

rd: Reg

rs1: Reg

rs2: Reg

Sha512Sum1r

Fields

rd: Reg

rs1: Reg

rs2: Reg

Trait Implementations

impl<Reg: Clone> Clone for Rv32ZknhInstruction<Reg>

fn clone(&self) -> Rv32ZknhInstruction<Reg>

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<Reg: Debug> Debug for Rv32ZknhInstruction<Reg>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<Reg> Display for Rv32ZknhInstruction<Reg>

where Reg: Display,

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<Reg> Instruction for Rv32ZknhInstruction<Reg>

where Reg: Register<Type = u32>,

type Reg = Reg

A register type used by the instruction

fn try_decode(instruction: u32) -> Option<Self>

Try to decode a single valid instruction

fn alignment() -> u8

Instruction alignment in bytes

fn size(&self) -> u8

Instruction size in bytes

impl<Reg: PartialEq> PartialEq for Rv32ZknhInstruction<Reg>

fn eq(&self, other: &Rv32ZknhInstruction<Reg>) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl<Reg: Copy> Copy for Rv32ZknhInstruction<Reg>

impl<Reg: Eq> Eq for Rv32ZknhInstruction<Reg>

impl<Reg> StructuralPartialEq for Rv32ZknhInstruction<Reg>