Enum Rv32ZkndInstruction 

pub enum Rv32ZkndInstruction<Reg> {
    Aes32Dsi {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
        bs: Rv32AesBs,
    },
    Aes32Dsmi {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
        bs: Rv32AesBs,
    },
}

RISC-V RV32 Zknd instructions (AES decryption)

Variants

Aes32Dsi

AES final round decryption step: InvSubBytes on one byte of rs2, rotated to the byte lane selected by bs, XOR’d into rs1.

rd = rs1 ^ rol32(INV_SBOX[(rs2 >> (bs*8)) & 0xff] as u32, bs*8)

Fields

rd: Reg

rs1: Reg

rs2: Reg

bs: Rv32AesBs

Aes32Dsmi

AES middle round decryption step: InvSubBytes + partial InvMixColumns on one byte of rs2, rotated to the byte lane selected by bs, XOR’d into rs1.

rd = rs1 ^ rol32(InvMixColByte(INV_SBOX[(rs2 >> (bs*8)) & 0xff]), bs*8)

Fields

rd: Reg

rs1: Reg

rs2: Reg

bs: Rv32AesBs

Trait Implementations

impl<Reg: Clone> Clone for Rv32ZkndInstruction<Reg>

fn clone(&self) -> Rv32ZkndInstruction<Reg>

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<Reg: Debug> Debug for Rv32ZkndInstruction<Reg>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<Reg> Display for Rv32ZkndInstruction<Reg>

where Reg: Display,

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<Reg> Instruction for Rv32ZkndInstruction<Reg>

where Reg: Register<Type = u32>,

Encoding layout (R-type, opcode 0x33, funct3 0x0):

[31:30] bs       - 2-bit byte select
[29:25] funct5   - 0b10101 (aes32dsi) / 0b10111 (aes32dsmi)
[24:20] rs2
[19:15] rs1
[14:12] funct3   - 0b000
[11:7]  rd
[6:0]   opcode   - 0b0110011 (OP)

Ratified match/mask values (from riscv-opcodes): MATCH_AES32DSI = 0x2a000033, MASK_AES32DSI = 0x3e00707f MATCH_AES32DSMI = 0x2e000033, MASK_AES32DSMI = 0x3e00707f

rd and rs1 are independent fields. The assembler convention places the accumulator in both rd and rs1 (the rt pattern), but the hardware does not require rd == rs1 and the decoder must not enforce it.

type Reg = Reg

A register type used by the instruction

fn try_decode(instruction: u32) -> Option<Self>

Try to decode a single valid instruction

fn alignment() -> u8

Instruction alignment in bytes

fn size(&self) -> u8

Instruction size in bytes

impl<Reg: PartialEq> PartialEq for Rv32ZkndInstruction<Reg>

fn eq(&self, other: &Rv32ZkndInstruction<Reg>) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl<Reg: Copy> Copy for Rv32ZkndInstruction<Reg>

impl<Reg: Eq> Eq for Rv32ZkndInstruction<Reg>

impl<Reg> StructuralPartialEq for Rv32ZkndInstruction<Reg>