Enum Rv32ZkndInstruction 

#[repr(u16, align(4))]
pub enum Rv32ZkndInstruction<Hart>
where
    Hart: HartConfig,
{
    Aes32Dsi {
        rs1: Hart::Reg,
        rs2: Hart::Reg,
        rd: Hart::Reg,
        bs: Rv32AesBs,
    },
    Aes32Dsmi {
        rs1: Hart::Reg,
        rs2: Hart::Reg,
        rd: Hart::Reg,
        bs: Rv32AesBs,
    },
}

RISC-V RV32 Zknd instructions (AES decryption)

Variants

Aes32Dsi

AES final round decryption step: InvSubBytes on one byte of rs2, rotated to the byte lane selected by bs, XOR’d into rs1.

rd = rs1 ^ rol32(INV_SBOX[(rs2 >> (bs*8)) & 0xff] as u32, bs*8)

Fields

rs1: Hart::Reg

rs2: Hart::Reg

rd: Hart::Reg

bs: Rv32AesBs

Aes32Dsmi

AES middle round decryption step: InvSubBytes + partial InvMixColumns on one byte of rs2, rotated to the byte lane selected by bs, XOR’d into rs1.

rd = rs1 ^ rol32(InvMixColByte(INV_SBOX[(rs2 >> (bs*8)) & 0xff]), bs*8)

Fields

rs1: Hart::Reg

rs2: Hart::Reg

rd: Hart::Reg

bs: Rv32AesBs

Trait Implementations

impl<Hart> Clone for Rv32ZkndInstruction<Hart>

where Hart: HartConfig + Clone, Hart::Reg: Clone,

fn clone(&self) -> Rv32ZkndInstruction<Hart>

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<Hart> Copy for Rv32ZkndInstruction<Hart>

where Hart: HartConfig + Copy, Hart::Reg: Copy,

impl<Hart> Debug for Rv32ZkndInstruction<Hart>

where Hart: HartConfig + Debug, Hart::Reg: Debug,

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<Reg, Hart> Display for Rv32ZkndInstruction<Hart>

where Reg: Display, Hart: HartConfig<Reg = Reg>,

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<Hart> Eq for Rv32ZkndInstruction<Hart>

where Hart: HartConfig + Eq, Hart::Reg: Eq,

impl<Reg, Hart> Instruction for Rv32ZkndInstruction<Hart>

where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

Encoding layout (R-type, opcode 0x33, funct3 0x0):

[31:30] bs       - 2-bit byte select
[29:25] funct5   - 0b1_0101 (aes32dsi) / 0b1_0111 (aes32dsmi)
[24:20] rs2
[19:15] rs1
[14:12] funct3   - 0b000
[11:7]  rd
[6:0]   opcode   - 0b011_0011 (OP)

Ratified match/mask values (from riscv-opcodes): MATCH_AES32DSI = 0x2a00_0033, MASK_AES32DSI = 0x3e00_707f MATCH_AES32DSMI = 0x2e00_0033, MASK_AES32DSMI = 0x3e00_707f

rd and rs1 are independent fields. The assembler convention places the accumulator in both rd and rs1 (the rt pattern), but the hardware does not require rd == rs1 and the decoder must not enforce it.

const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]

All implemented extensions, including this instruction itself, with their ISA extensions.

const OWN_ISA_EXTENSIONS: &'static [IsaExtension]

ISA extensions defined by this instruction enum itself, without inherited ones.

const ALIGNMENT: u8

Instruction alignment in bytes, also known as IALIGN

type Hart = Hart

Hart configuration of the implementation

fn try_decode(instruction: u32) -> Option<Self>

Try to decode a single valid instruction

fn size(&self) -> u8

Instruction size in bytes

const ISA_STRING: &'static str = _

ISA string as used in the Tag_RISCV_arch attribute of ELF files, for example, rv64i2p1_m2p0_zmmul1p0.

fn implements_extension<E>() -> bool

where E: Instruction<Hart = Self::Hart>,

Checks whether this instruction implements the given extension, see Self::IMPLEMENTED_EXTENSIONS for details

impl<Hart> PartialEq for Rv32ZkndInstruction<Hart>

where Hart: HartConfig + PartialEq, Hart::Reg: PartialEq,

fn eq(&self, other: &Rv32ZkndInstruction<Hart>) -> bool

Equality operator ==.

fn ne(&self, other: &Rhs) -> bool

Inequality operator !=.

impl<Hart> StructuralPartialEq for Rv32ZkndInstruction<Hart>

where Hart: HartConfig + PartialEq, Hart::Reg: PartialEq,