pub enum Rv32ZknInstruction<Reg> {
Show 30 variants
Andn {
rd: Reg,
rs1: Reg,
rs2: Reg,
},
Orn {
rd: Reg,
rs1: Reg,
rs2: Reg,
},
Xnor {
rd: Reg,
rs1: Reg,
rs2: Reg,
},
Rol {
rd: Reg,
rs1: Reg,
rs2: Reg,
},
Ror {
rd: Reg,
rs1: Reg,
rs2: Reg,
},
Rori {
rd: Reg,
rs1: Reg,
shamt: u8,
},
Rev8 {
rd: Reg,
rs1: Reg,
},
Pack {
rd: Reg,
rs1: Reg,
rs2: Reg,
},
Packh {
rd: Reg,
rs1: Reg,
rs2: Reg,
},
Brev8 {
rd: Reg,
rs1: Reg,
},
Zip {
rd: Reg,
rs1: Reg,
},
Unzip {
rd: Reg,
rs1: Reg,
},
Clmul {
rd: Reg,
rs1: Reg,
rs2: Reg,
},
Clmulh {
rd: Reg,
rs1: Reg,
rs2: Reg,
},
Xperm4 {
rd: Reg,
rs1: Reg,
rs2: Reg,
},
Xperm8 {
rd: Reg,
rs1: Reg,
rs2: Reg,
},
Aes32Dsi {
rd: Reg,
rs1: Reg,
rs2: Reg,
bs: Rv32AesBs,
},
Aes32Dsmi {
rd: Reg,
rs1: Reg,
rs2: Reg,
bs: Rv32AesBs,
},
Aes32Esi {
rd: Reg,
rs1: Reg,
rs2: Reg,
bs: Rv32AesBs,
},
Aes32Esmi {
rd: Reg,
rs1: Reg,
rs2: Reg,
bs: Rv32AesBs,
},
Sha256Sig0 {
rd: Reg,
rs1: Reg,
},
Sha256Sig1 {
rd: Reg,
rs1: Reg,
},
Sha256Sum0 {
rd: Reg,
rs1: Reg,
},
Sha256Sum1 {
rd: Reg,
rs1: Reg,
},
Sha512Sig0h {
rd: Reg,
rs1: Reg,
rs2: Reg,
},
Sha512Sig0l {
rd: Reg,
rs1: Reg,
rs2: Reg,
},
Sha512Sig1h {
rd: Reg,
rs1: Reg,
rs2: Reg,
},
Sha512Sig1l {
rd: Reg,
rs1: Reg,
rs2: Reg,
},
Sha512Sum0r {
rd: Reg,
rs1: Reg,
rs2: Reg,
},
Sha512Sum1r {
rd: Reg,
rs1: Reg,
rs2: Reg,
},
}Expand description
RISC-V RV32 Zkn (Zbkb + Zbkc + Zbkx + Zknd + Zkne + Zknh) instruction
Variants§
Andn
Orn
Xnor
Rol
Ror
Rori
Rev8
Pack
Pack low 16 bits of rs1 into rd[15:0], low 16 bits of rs2 into rd[31:16]
Packh
Pack low 8 bits of rs1 into rd[7:0], low 8 bits of rs2 into rd[15:8]
Brev8
Reverse bits in each byte of rs1
Zip
Bit-interleave: scatter lower-half bits of rs1 to even positions, upper-half bits to odd
positions
Unzip
Inverse of zip: gather even-position bits of rs1 to lower half, odd-position bits to upper
half
Clmul
Clmulh
Xperm4
Xperm8
Aes32Dsi
AES final round decryption step: InvSubBytes on one byte of rs2, rotated to the byte lane selected by bs, XOR’d into rs1.
rd = rs1 ^ rol32(INV_SBOX[(rs2 >> (bs*8)) & 0xff] as u32, bs*8)
Aes32Dsmi
AES middle round decryption step: InvSubBytes + partial InvMixColumns on one byte of rs2, rotated to the byte lane selected by bs, XOR’d into rs1.
rd = rs1 ^ rol32(InvMixColByte(INV_SBOX[(rs2 >> (bs*8)) & 0xff]), bs*8)
Aes32Esi
AES final round encryption step: SubBytes on one byte of rs2, rotated to the byte lane selected by bs, XOR’d into rs1.
rd = rs1 ^ rol32(SBOX[(rs2 >> (bs*8)) & 0xff] as u32, bs*8)
Aes32Esmi
AES middle round encryption step: SubBytes + partial MixColumns on one byte of rs2, rotated to the byte lane selected by bs, XOR’d into rs1.
rd = rs1 ^ rol32(MixColByte(SBOX[(rs2 >> (bs*8)) & 0xff]), bs*8)
Sha256Sig0
Sha256Sig1
Sha256Sum0
Sha256Sum1
Sha512Sig0h
Sha512Sig0l
Sha512Sig1h
Sha512Sig1l
Sha512Sum0r
Sha512Sum1r
Trait Implementations§
Source§impl<Reg: Clone> Clone for Rv32ZknInstruction<Reg>
impl<Reg: Clone> Clone for Rv32ZknInstruction<Reg>
Source§fn clone(&self) -> Rv32ZknInstruction<Reg>
fn clone(&self) -> Rv32ZknInstruction<Reg>
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read more