Enum Rv32ZcmpInstruction 

pub enum Rv32ZcmpInstruction<Reg> {
    CAddi4spn {
        rd: Reg,
        nzuimm: u16,
        /* private fields */
    },
    CLw {
        rs1: Reg,
        rd: Reg,
        uimm: u8,
        /* private fields */
    },
    CSw {
        rs1: Reg,
        rs2: Reg,
        uimm: u8,
    },
    CNop { /* private fields */ },
    CAddi {
        rd: Reg,
        nzimm: i8,
        /* private fields */
    },
    CJal {
        imm: i16,
        /* private fields */
    },
    CLi {
        rd: Reg,
        imm: i8,
        /* private fields */
    },
    CAddi16sp {
        nzimm: i16,
        /* private fields */
    },
    CLui {
        rd: Reg,
        nzimm: I24,
        /* private fields */
    },
    CSrli {
        rd: Reg,
        shamt: u8,
        /* private fields */
    },
    CSrai {
        rd: Reg,
        shamt: u8,
        /* private fields */
    },
    CAndi {
        rd: Reg,
        imm: i8,
        /* private fields */
    },
    CSub {
        rs2: Reg,
        rd: Reg,
        /* private fields */
    },
    CXor {
        rs2: Reg,
        rd: Reg,
        /* private fields */
    },
    COr {
        rs2: Reg,
        rd: Reg,
        /* private fields */
    },
    CAnd {
        rs2: Reg,
        rd: Reg,
        /* private fields */
    },
    CJ {
        imm: i16,
        /* private fields */
    },
    CBeqz {
        rs1: Reg,
        imm: i16,
        /* private fields */
    },
    CBnez {
        rs1: Reg,
        imm: i16,
        /* private fields */
    },
    CSlli {
        rd: Reg,
        shamt: u8,
        /* private fields */
    },
    CLwsp {
        rd: Reg,
        uimm: u8,
        /* private fields */
    },
    CJr {
        rs1: Reg,
        /* private fields */
    },
    CMv {
        rs2: Reg,
        rd: Reg,
        /* private fields */
    },
    CEbreak { /* private fields */ },
    CJalr {
        rs1: Reg,
        /* private fields */
    },
    CAdd {
        rs2: Reg,
        rd: Reg,
        /* private fields */
    },
    CSwsp {
        rs2: Reg,
        uimm: u8,
        /* private fields */
    },
    CUnimp { /* private fields */ },
    CmPush {
        urlist: ZcmpUrlist<Reg>,
        stack_adj: u8,
        /* private fields */
    },
    CmPop {
        urlist: ZcmpUrlist<Reg>,
        stack_adj: u8,
        /* private fields */
    },
    CmPopretz {
        urlist: ZcmpUrlist<Reg>,
        stack_adj: u8,
        /* private fields */
    },
    CmPopret {
        urlist: ZcmpUrlist<Reg>,
        stack_adj: u8,
        /* private fields */
    },
    CmMva01s {
        rs1: Reg,
        rs2: Reg,
    },
    CmMvsa01 {
        rs1: Reg,
        rs2: Reg,
    },
}

Zcmp compressed instruction set

Variants

CAddi4spn

C.ADDI4SPN rd’ = sp + nzuimm (nzuimm != 0)

Fields

rd: Reg

nzuimm: u16

CLw

C.LW rd’ = sext(mem32[rs1’ + uimm])

Fields

rs1: Reg

rd: Reg

uimm: u8

CSw

C.SW mem32[rs1’ + uimm] = rs2’

Fields

rs1: Reg

rs2: Reg

uimm: u8

CNop

C.NOP (ADDI x0, x0, 0 with rd==x0 and nzimm==0)

CAddi

C.ADDI rd += nzimm (rd != x0)

Fields

rd: Reg

nzimm: i8

CJal

C.JAL ra = pc+2; pc += imm

Fields

imm: i16

CLi

C.LI rd = sext(imm) (rd=x0 is a HINT)

Fields

rd: Reg

imm: i8

CAddi16sp

C.ADDI16SP sp += nzimm (nzimm != 0)

Fields

nzimm: i16

CLui

C.LUI rd = sext(nzimm << 12) (rd != x0, rd != x2, nzimm != 0)

Fields

rd: Reg

nzimm: I24

CSrli

C.SRLI rd’ >>= shamt (logical, 5-bit shamt; shamt=0 is a HINT)

Fields

rd: Reg

shamt: u8

CSrai

C.SRAI rd’ >>= shamt (arithmetic, 5-bit shamt; shamt=0 is a HINT)

Fields

rd: Reg

shamt: u8

CAndi

C.ANDI rd’ &= sext(imm)

Fields

rd: Reg

imm: i8

CSub

C.SUB rd’ -= rs2’

Fields

rs2: Reg

rd: Reg

CXor

C.XOR rd’ ^= rs2’

Fields

rs2: Reg

rd: Reg

COr

C.OR rd’ |= rs2’

Fields

rs2: Reg

rd: Reg

CAnd

C.AND rd’ &= rs2’

Fields

rs2: Reg

rd: Reg

CJ

C.J pc += sext(imm)

Fields

imm: i16

CBeqz

C.BEQZ if rs1’ == 0: pc += sext(imm)

Fields

rs1: Reg

imm: i16

CBnez

C.BNEZ if rs1’ != 0: pc += sext(imm)

Fields

rs1: Reg

imm: i16

CSlli

C.SLLI rd <<= shamt (5-bit shamt; rd=x0 or shamt=0 is a HINT)

Fields

rd: Reg

shamt: u8

CLwsp

C.LWSP rd = sext(mem32[sp + uimm]) (rd != x0)

Fields

rd: Reg

uimm: u8

CJr

C.JR pc = rs1 (rs1 != x0)

Fields

rs1: Reg

CMv

C.MV rd = rs2 (rs2 != x0; rd=x0 is a HINT)

Fields

rs2: Reg

rd: Reg

CEbreak

C.EBREAK

CJalr

C.JALR ra = pc+2; pc = rs1 (rs1 != x0)

Fields

rs1: Reg

CAdd

C.ADD rd += rs2 (rs2 != x0; rd=x0 is a HINT)

Fields

rs2: Reg

rd: Reg

CSwsp

C.SWSP mem32[sp + uimm] = rs2

Fields

rs2: Reg

uimm: u8

CUnimp

CmPush

CM.PUSH - push reg_list, decrement sp by stack_adj

stack_adj = urlist.stack_adj_base() + spimm * 16 from the encoding.

Fields

urlist: ZcmpUrlist<Reg>

stack_adj: u8

CmPop

CM.POP - pop reg_list, increment sp by stack_adj (no return)

Fields

urlist: ZcmpUrlist<Reg>

stack_adj: u8

CmPopretz

CM.POPRETZ - pop reg_list, set a0=0, increment sp, return

Fields

urlist: ZcmpUrlist<Reg>

stack_adj: u8

CmPopret

CM.POPRET - pop reg_list, increment sp, return

Fields

urlist: ZcmpUrlist<Reg>

stack_adj: u8

CmMva01s

CM.MVA01S - a0 = r1s’, a1 = r2s’.

The fields are called both r1s/r2s and rs1/rs2 in the spec, rs1/rs2 is used here for consistency with other instructions.

Fields

rs1: Reg

rs2: Reg

CmMvsa01

CM.MVSA01 - r1s’ = a0, r2s’ = a1 (r1s’ != r2s’).

The fields are called both r1s/r2s and rs1/rs2 in the spec, rs1/rs2 is used here for consistency with other instructions.

Fields

rs1: Reg

rs2: Reg

Trait Implementations

impl<Reg: Clone> Clone for Rv32ZcmpInstruction<Reg>

fn clone(&self) -> Rv32ZcmpInstruction<Reg>

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<Reg: Debug> Debug for Rv32ZcmpInstruction<Reg>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<Reg> Display for Rv32ZcmpInstruction<Reg>

where Reg: Register,

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<Reg> Instruction for Rv32ZcmpInstruction<Reg>

where Reg: Register<Type = u32> + ZcmpRegister<Type = u32>,

type Reg = Reg

A register type used by the instruction

fn try_decode(instruction: u32) -> Option<Self>

Try to decode a single valid instruction

fn alignment() -> u8

Instruction alignment in bytes

fn size(&self) -> u8

Instruction size in bytes

impl<Reg: PartialEq> PartialEq for Rv32ZcmpInstruction<Reg>

fn eq(&self, other: &Rv32ZcmpInstruction<Reg>) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl<Reg: Copy> Copy for Rv32ZcmpInstruction<Reg>

impl<Reg: Eq> Eq for Rv32ZcmpInstruction<Reg>

impl<Reg> StructuralPartialEq for Rv32ZcmpInstruction<Reg>