Enum Rv32ZalasrInstruction 

pub enum Rv32ZalasrInstruction<Hart>
where
    Hart: HartConfig,
{
    LbAq {
        rs1: Hart::Reg,
        rd: Hart::Reg,
        rl: bool,
        /* private fields */
    },
    LhAq {
        rs1: Hart::Reg,
        rd: Hart::Reg,
        rl: bool,
        /* private fields */
    },
    LwAq {
        rs1: Hart::Reg,
        rd: Hart::Reg,
        rl: bool,
        /* private fields */
    },
    SbRl {
        rs1: Hart::Reg,
        rs2: Hart::Reg,
        aq: bool,
    },
    ShRl {
        rs1: Hart::Reg,
        rs2: Hart::Reg,
        aq: bool,
    },
    SwRl {
        rs1: Hart::Reg,
        rs2: Hart::Reg,
        aq: bool,
    },
}

RISC-V RV32 Zalasr instruction (Load-Acquire/Store-Release).

Load-acquire instructions always carry an acquire annotation (not stored as a field since it is always true), plus an optional release annotation stored in rl. Store-release instructions always carry a release annotation (not stored as a field since it is always true), plus an optional acquire annotation stored in aq.

Variants

LbAq

Load-acquire byte

Fields

rs1: Hart::Reg

rd: Hart::Reg

rl: bool

LhAq

Load-acquire halfword

Fields

rs1: Hart::Reg

rd: Hart::Reg

rl: bool

LwAq

Load-acquire word

Fields

rs1: Hart::Reg

rd: Hart::Reg

rl: bool

SbRl

Store-release byte

Fields

rs1: Hart::Reg

rs2: Hart::Reg

aq: bool

ShRl

Store-release halfword

Fields

rs1: Hart::Reg

rs2: Hart::Reg

aq: bool

SwRl

Store-release word

Fields

rs1: Hart::Reg

rs2: Hart::Reg

aq: bool

Trait Implementations

impl<Hart> Clone for Rv32ZalasrInstruction<Hart>

where Hart: HartConfig + Clone, Hart::Reg: Clone,

fn clone(&self) -> Rv32ZalasrInstruction<Hart>

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<Hart> Copy for Rv32ZalasrInstruction<Hart>

where Hart: HartConfig + Copy, Hart::Reg: Copy,

impl<Hart> Debug for Rv32ZalasrInstruction<Hart>

where Hart: HartConfig + Debug, Hart::Reg: Debug,

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<Reg, Hart> Display for Rv32ZalasrInstruction<Hart>

where Reg: Display, Hart: HartConfig<Reg = Reg>,

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<Hart> Eq for Rv32ZalasrInstruction<Hart>

where Hart: HartConfig + Eq, Hart::Reg: Eq,

impl<Reg, Hart> Instruction for Rv32ZalasrInstruction<Hart>

where Reg: Register<Type = u32>, Hart: HartConfig<Reg = Reg>,

const IMPLEMENTED_EXTENSIONS: &'static [ImplementedExtension]

All implemented extensions, including this instruction itself, with their ISA extensions.

const OWN_ISA_EXTENSIONS: &'static [IsaExtension]

ISA extensions defined by this instruction enum itself, without inherited ones.

const ALIGNMENT: u8

Instruction alignment in bytes, also known as IALIGN

type Hart = Hart

Hart configuration of the implementation

fn try_decode(instruction: u32) -> Option<Self>

Try to decode a single valid instruction

fn size(&self) -> u8

Instruction size in bytes

const ISA_STRING: &'static str = _

ISA string as used in the Tag_RISCV_arch attribute of ELF files, for example, rv64i2p1_m2p0_zmmul1p0.

fn implements_extension<E>() -> bool

where E: Instruction<Hart = Self::Hart>,

Checks whether this instruction implements the given extension, see Self::IMPLEMENTED_EXTENSIONS for details

impl<Hart> PartialEq for Rv32ZalasrInstruction<Hart>

where Hart: HartConfig + PartialEq, Hart::Reg: PartialEq,

fn eq(&self, other: &Rv32ZalasrInstruction<Hart>) -> bool

Equality operator ==.

fn ne(&self, other: &Rhs) -> bool

Inequality operator !=.

impl<Hart> StructuralPartialEq for Rv32ZalasrInstruction<Hart>

where Hart: HartConfig + PartialEq, Hart::Reg: PartialEq,