Enum Rv32ZacasInstruction 

#[repr(u16, align(4))]
pub enum Rv32ZacasInstruction<Reg> {
    Amoswap {
        rs1: Reg,
        rs2: Reg,
        rd: Reg,
        aq: bool,
        rl: bool,
    },
    Amoadd {
        rs1: Reg,
        rs2: Reg,
        rd: Reg,
        aq: bool,
        rl: bool,
    },
    Amoxor {
        rs1: Reg,
        rs2: Reg,
        rd: Reg,
        aq: bool,
        rl: bool,
    },
    Amoand {
        rs1: Reg,
        rs2: Reg,
        rd: Reg,
        aq: bool,
        rl: bool,
    },
    Amoor {
        rs1: Reg,
        rs2: Reg,
        rd: Reg,
        aq: bool,
        rl: bool,
    },
    Amomin {
        rs1: Reg,
        rs2: Reg,
        rd: Reg,
        aq: bool,
        rl: bool,
    },
    Amomax {
        rs1: Reg,
        rs2: Reg,
        rd: Reg,
        aq: bool,
        rl: bool,
    },
    Amominu {
        rs1: Reg,
        rs2: Reg,
        rd: Reg,
        aq: bool,
        rl: bool,
    },
    Amomaxu {
        rs1: Reg,
        rs2: Reg,
        rd: Reg,
        aq: bool,
        rl: bool,
    },
    AmocasW {
        rs1: Reg,
        rs2: Reg,
        rd: Reg,
        aq: bool,
        rl: bool,
    },
    AmocasD {
        rs1: Reg,
        rs2: Reg,
        rd: Reg,
        rd_hi: Reg,
        rs2_hi: Reg,
        aq: bool,
        rl: bool,
    },
}

RISC-V RV32 Zacas instruction (Atomic Compare-and-Swap)

Variants

Amoswap

Fields

rs1: Reg

rs2: Reg

rd: Reg

aq: bool

rl: bool

Amoadd

Fields

rs1: Reg

rs2: Reg

rd: Reg

aq: bool

rl: bool

Amoxor

Fields

rs1: Reg

rs2: Reg

rd: Reg

aq: bool

rl: bool

Amoand

Fields

rs1: Reg

rs2: Reg

rd: Reg

aq: bool

rl: bool

Amoor

Fields

rs1: Reg

rs2: Reg

rd: Reg

aq: bool

rl: bool

Amomin

Fields

rs1: Reg

rs2: Reg

rd: Reg

aq: bool

rl: bool

Amomax

Fields

rs1: Reg

rs2: Reg

rd: Reg

aq: bool

rl: bool

Amominu

Fields

rs1: Reg

rs2: Reg

rd: Reg

aq: bool

rl: bool

Amomaxu

Fields

rs1: Reg

rs2: Reg

rd: Reg

aq: bool

rl: bool

AmocasW

Compare-and-swap word

Fields

rs1: Reg

rs2: Reg

rd: Reg

aq: bool

rl: bool

AmocasD

Compare-and-swap doubleword, using register pairs (rd, rd_hi) and (rs2, rs2_hi) since RV32 registers are only 32 bits wide

Fields

rs1: Reg

rs2: Reg

rd: Reg

rd_hi: Reg

rs2_hi: Reg

aq: bool

rl: bool

Trait Implementations

impl<Reg: Clone> Clone for Rv32ZacasInstruction<Reg>

fn clone(&self) -> Rv32ZacasInstruction<Reg>

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<Reg: Copy> Copy for Rv32ZacasInstruction<Reg>

impl<Reg: Debug> Debug for Rv32ZacasInstruction<Reg>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<Reg> Display for Rv32ZacasInstruction<Reg>

where Reg: Display + Copy,

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<Reg: Eq> Eq for Rv32ZacasInstruction<Reg>

impl<Reg> Instruction for Rv32ZacasInstruction<Reg>

where Reg: Register<Type = u32>,

const IMPLEMENTED_EXTENSIONS: &'static [TypeId]

Types of all fully implemented extensions.

type Reg = Reg

A register type used by the instruction

fn try_decode(instruction: u32) -> Option<Self>

Try to decode a single valid instruction

fn alignment() -> u8

Instruction alignment in bytes

fn size(&self) -> u8

Instruction size in bytes

fn implements_extension<E>() -> bool

where E: Instruction<Reg = Self::Reg>,

Checks whether this instruction implements the given extension

impl<Reg: PartialEq> PartialEq for Rv32ZacasInstruction<Reg>

fn eq(&self, other: &Rv32ZacasInstruction<Reg>) -> bool

Equality operator ==.

fn ne(&self, other: &Rhs) -> bool

Inequality operator !=.

impl<Reg: PartialEq> StructuralPartialEq for Rv32ZacasInstruction<Reg>