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Rv32Instruction

ab_riscv_primitives::instructions::rv32

Enum Rv32Instruction

pub enum Rv32Instruction<Reg> {
Show 42 variants    Add {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sub {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sll {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Slt {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sltu {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Xor {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Srl {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sra {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Or {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    And {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Addi {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Slti {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Sltiu {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Xori {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Ori {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Andi {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Slli {
        rd: Reg,
        rs1: Reg,
        shamt: u8,
    },
    Srli {
        rd: Reg,
        rs1: Reg,
        shamt: u8,
    },
    Srai {
        rd: Reg,
        rs1: Reg,
        shamt: u8,
    },
    Lb {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Lh {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Lw {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Lbu {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Lhu {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Jalr {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Sb {
        rs2: Reg,
        rs1: Reg,
        imm: i16,
    },
    Sh {
        rs2: Reg,
        rs1: Reg,
        imm: i16,
    },
    Sw {
        rs2: Reg,
        rs1: Reg,
        imm: i16,
    },
    Beq {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Bne {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Blt {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Bge {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Bltu {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Bgeu {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Lui {
        rd: Reg,
        imm: i32,
    },
    Auipc {
        rd: Reg,
        imm: i32,
    },
    Jal {
        rd: Reg,
        imm: i32,
    },
    Fence {
        pred: u8,
        succ: u8,
    },
    FenceTso,
    Ecall,
    Ebreak,
    Unimp,
}

Expand description

RISC-V RV32 instruction

Variants§

Add

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Sub

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Sll

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Slt

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Sltu

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Xor

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Srl

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Sra

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Or

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

And

Fields

§rd: Reg

§rs1: Reg

§rs2: Reg

Addi

Fields

§rd: Reg

§rs1: Reg

§imm: i16

Slti

Fields

§rd: Reg

§rs1: Reg

§imm: i16

Sltiu

Fields

§rd: Reg

§rs1: Reg

§imm: i16

Xori

Fields

§rd: Reg

§rs1: Reg

§imm: i16

Ori

Fields

§rd: Reg

§rs1: Reg

§imm: i16

Andi

Fields

§rd: Reg

§rs1: Reg

§imm: i16

Slli

Fields

§rd: Reg

§rs1: Reg

§shamt: u8

Srli

Fields

§rd: Reg

§rs1: Reg

§shamt: u8

Srai

Fields

§rd: Reg

§rs1: Reg

§shamt: u8

Lb

Fields

§rd: Reg

§rs1: Reg

§imm: i16

Lh

Fields

§rd: Reg

§rs1: Reg

§imm: i16

Lw

Fields

§rd: Reg

§rs1: Reg

§imm: i16

Lbu

Fields

§rd: Reg

§rs1: Reg

§imm: i16

Lhu

Fields

§rd: Reg

§rs1: Reg

§imm: i16

Jalr

Fields

§rd: Reg

§rs1: Reg

§imm: i16

Sb

Fields

§rs2: Reg

§rs1: Reg

§imm: i16

Sh

Fields

§rs2: Reg

§rs1: Reg

§imm: i16

Sw

Fields

§rs2: Reg

§rs1: Reg

§imm: i16

Beq

Fields

§rs1: Reg

§rs2: Reg

§imm: i32

Bne

Fields

§rs1: Reg

§rs2: Reg

§imm: i32

Blt

Fields

§rs1: Reg

§rs2: Reg

§imm: i32

Bge

Fields

§rs1: Reg

§rs2: Reg

§imm: i32

Bltu

Fields

§rs1: Reg

§rs2: Reg

§imm: i32

Bgeu

Fields

§rs1: Reg

§rs2: Reg

§imm: i32

Lui

Fields

§rd: Reg

§imm: i32

Auipc

Fields

§rd: Reg

§imm: i32

Jal

Fields

§rd: Reg

§imm: i32

Fence

Fields

§pred: u8

§succ: u8

FenceTso

Ecall

Ebreak

Unimp

Trait Implementations§

impl<Reg: Clone> Clone for Rv32Instruction<Reg>

fn clone(&self) -> Rv32Instruction<Reg>

Returns a duplicate of the value. Read more

1.0.0 · Source§

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more

impl<Reg: Debug> Debug for Rv32Instruction<Reg>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more

impl<Reg> Display for Rv32Instruction<Reg>
where Reg: Display,

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more

impl<Reg> Instruction for Rv32Instruction<Reg>
where Reg: Register<Type = u32>,

type Reg = Reg

A register type used by the instruction

fn try_decode(instruction: u32) -> Option<Self>

Try to decode a single valid instruction

fn alignment() -> u8

Instruction alignment in bytes

fn size(&self) -> u8

Instruction size in bytes

impl<Reg: PartialEq> PartialEq for Rv32Instruction<Reg>

fn eq(&self, other: &Rv32Instruction<Reg>) -> bool

Tests for self and other values to be equal, and is used by ==.

1.0.0 · Source§

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl<Reg: Copy> Copy for Rv32Instruction<Reg>

impl<Reg: Eq> Eq for Rv32Instruction<Reg>

impl<Reg> StructuralPartialEq for Rv32Instruction<Reg>

Auto Trait Implementations§

impl<Reg> Freeze for Rv32Instruction<Reg>
where Reg: Freeze,

impl<Reg> RefUnwindSafe for Rv32Instruction<Reg>
where Reg: RefUnwindSafe,

impl<Reg> Send for Rv32Instruction<Reg>
where Reg: Send,

impl<Reg> Sync for Rv32Instruction<Reg>
where Reg: Sync,

impl<Reg> Unpin for Rv32Instruction<Reg>
where Reg: Unpin,

impl<Reg> UnsafeUnpin for Rv32Instruction<Reg>
where Reg: UnsafeUnpin,

impl<Reg> UnwindSafe for Rv32Instruction<Reg>
where Reg: UnwindSafe,

Blanket Implementations§

impl<T> Any for T
where T: 'static + ?Sized,

fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more

impl<T> Borrow<T> for T
where T: ?Sized,

fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more

impl<T> BorrowMut<T> for T
where T: ?Sized,

fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more

impl<T> CloneToUninit for T
where T: Clone,

unsafe fn clone_to_uninit(&self, dest: *mut u8)

🔬This is a nightly-only experimental API. (clone_to_uninit)

Performs copy-assignment from self to dest. Read more

impl<T> From<T> for T

fn from(t: T) -> T

Returns the argument unchanged.

impl<T, U> Into<U> for T
where U: From<T>,

fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

impl<T> ToOwned for T
where T: Clone,

type Owned = T

The resulting type after obtaining ownership.

fn to_owned(&self) -> T

Creates owned data from borrowed data, usually by cloning. Read more

fn clone_into(&self, target: &mut T)

Uses borrowed data to replace owned data, usually by cloning. Read more

impl<T> ToString for T
where T: Display + ?Sized,

fn to_string(&self) -> String

Converts the given value to a String. Read more

impl<T, U> TryFrom<U> for T
where U: Into<T>,

type Error = Infallible

The type returned in the event of a conversion error.

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.

impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.