Enum Rv64Instruction

Source

pub enum Rv64Instruction<Reg> {
Show 54 variants    Add {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sub {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sll {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Slt {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sltu {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Xor {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Srl {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sra {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Or {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    And {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Addw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Subw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sllw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Srlw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sraw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Addi {
        rd: Reg,
        rs1: Reg,
        imm: i32,
    },
    Slti {
        rd: Reg,
        rs1: Reg,
        imm: i32,
    },
    Sltiu {
        rd: Reg,
        rs1: Reg,
        imm: i32,
    },
    Xori {
        rd: Reg,
        rs1: Reg,
        imm: i32,
    },
    Ori {
        rd: Reg,
        rs1: Reg,
        imm: i32,
    },
    Andi {
        rd: Reg,
        rs1: Reg,
        imm: i32,
    },
    Slli {
        rd: Reg,
        rs1: Reg,
        shamt: u32,
    },
    Srli {
        rd: Reg,
        rs1: Reg,
        shamt: u32,
    },
    Srai {
        rd: Reg,
        rs1: Reg,
        shamt: u32,
    },
    Addiw {
        rd: Reg,
        rs1: Reg,
        imm: i32,
    },
    Slliw {
        rd: Reg,
        rs1: Reg,
        shamt: u32,
    },
    Srliw {
        rd: Reg,
        rs1: Reg,
        shamt: u32,
    },
    Sraiw {
        rd: Reg,
        rs1: Reg,
        shamt: u32,
    },
    Lb {
        rd: Reg,
        rs1: Reg,
        imm: i32,
    },
    Lh {
        rd: Reg,
        rs1: Reg,
        imm: i32,
    },
    Lw {
        rd: Reg,
        rs1: Reg,
        imm: i32,
    },
    Ld {
        rd: Reg,
        rs1: Reg,
        imm: i32,
    },
    Lbu {
        rd: Reg,
        rs1: Reg,
        imm: i32,
    },
    Lhu {
        rd: Reg,
        rs1: Reg,
        imm: i32,
    },
    Lwu {
        rd: Reg,
        rs1: Reg,
        imm: i32,
    },
    Jalr {
        rd: Reg,
        rs1: Reg,
        imm: i32,
    },
    Sb {
        rs2: Reg,
        rs1: Reg,
        imm: i32,
    },
    Sh {
        rs2: Reg,
        rs1: Reg,
        imm: i32,
    },
    Sw {
        rs2: Reg,
        rs1: Reg,
        imm: i32,
    },
    Sd {
        rs2: Reg,
        rs1: Reg,
        imm: i32,
    },
    Beq {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Bne {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Blt {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Bge {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Bltu {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Bgeu {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Lui {
        rd: Reg,
        imm: i32,
    },
    Auipc {
        rd: Reg,
        imm: i32,
    },
    Jal {
        rd: Reg,
        imm: i32,
    },
    Fence {
        pred: u8,
        succ: u8,
        fm: u8,
    },
    Ecall,
    Ebreak,
    Unimp,
    Invalid(u32),
}