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ExecutableInstructionCsr

ab_riscv_interpreter

Trait ExecutableInstructionCsr 

Source 
pub trait ExecutableInstructionCsr<Env>
where
    Self: Instruction,
{
    // Provided methods
    fn prepare_csr_read(
        env: &Env,
        csr_index: u16,
        will_write: bool,
        raw_value: <<Self as Instruction>::Reg as Register>::Type,
        output_value: &mut <<Self as Instruction>::Reg as Register>::Type,
    ) -> Result<bool, CsrError> { ... }
    fn prepare_csr_write(
        env: &mut Env,
        csr_index: u16,
        write_value: <<Self as Instruction>::Reg as Register>::Type,
        output_value: &mut <<Self as Instruction>::Reg as Register>::Type,
    ) -> Result<bool, CsrError> { ... }
}

Provided Methods§

Source

fn prepare_csr_read( env: &Env, csr_index: u16, will_write: bool, raw_value: <<Self as Instruction>::Reg as Register>::Type, output_value: &mut <<Self as Instruction>::Reg as Register>::Type, ) -> Result<bool, CsrError>

Prepare CSR read.

This method is called on each extension one by one with the raw_value (contents of the corresponding CSR register) and initially zero-initialized output_value. In return value every extension can accept (Ok(true)), ignore (Ok(false)) or reject (Err(CsrError)) read request. For accepted reads the extension must update output_value accordingly, which will be the value used by the Zicsr extension handler.

Some extensions will just copy raw_value to output value, others will copy only some bits or zero some bits of the raw_value, as required by the specification.

will_write indicates whether the CSR instruction performing this read will also perform a write immediately afterward (as part of the same instruction). It is always true for csrrw{,i}, and true for csrrs{,i}/csrrc{,i} unless their rs1/zimm operand is zero (in which case they are a pure read with no write). Some CSRs (e.g. Zkr’s seed) are only legal to access through a genuine read-write instruction and must reject the read when will_write is false.

If no extension returns Ok(true), the read operation is implicitly rejected as illegal access.

Source

fn prepare_csr_write( env: &mut Env, csr_index: u16, write_value: <<Self as Instruction>::Reg as Register>::Type, output_value: &mut <<Self as Instruction>::Reg as Register>::Type, ) -> Result<bool, CsrError>

Prepare CSR write.

This method is called on each extension one by one with write_value being prepared by the Zicsr extension handler. In return value every extension can accept (Ok(true)), ignore (Ok(false)) or reject (Err(CsrError)) write request. For accepted writes the extension must update output_value accordingly, which will be written to the corresponding CSR register.

Some extensions will just copy write_value to output value, others will copy some bits or zero some bits of the write_value, as required by the specification.

If no extension returns Ok(true), the write operation is implicitly rejected as illegal access.

Dyn Compatibility§

This trait is not dyn compatible.

In older versions of Rust, dyn compatibility was called "object safety".

Implementations on Foreign Types§

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32AInstruction<Reg>
where Reg: Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32BInstruction<Reg>
where Reg: Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32Instruction<Reg>
where Reg: Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32MInstruction<Reg>
where Reg: Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZaamoInstruction<Reg>
where Reg: Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZabhaInstruction<Reg>
where Reg: Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZacasInstruction<Reg>
where Reg: Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZalasrInstruction<Reg>
where Reg: Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZalrscInstruction<Reg>
where Reg: Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZbaInstruction<Reg>
where Reg: Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZbbInstruction<Reg>
where Reg: Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZbcInstruction<Reg>
where Reg: Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZbkbInstruction<Reg>
where Reg: Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZbkcInstruction<Reg>
where Reg: Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZbkxInstruction<Reg>
where Reg: Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZbsInstruction<Reg>
where Reg: Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZcaInstruction<Reg>
where Reg: Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZcbInstruction<Reg>
where Reg: Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZcmpInstruction<Reg>
where Reg: ZcmpRegister<Type = u32> + Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZknInstruction<Reg>
where Reg: Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZkndInstruction<Reg>
where Reg: Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZkneInstruction<Reg>
where Reg: Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZknhInstruction<Reg>
where Reg: Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZmmulInstruction<Reg>
where Reg: Register<Type = u32>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64AInstruction<Reg>
where Reg: Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64BInstruction<Reg>
where Reg: Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64Instruction<Reg>
where Reg: Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64MInstruction<Reg>
where Reg: Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64ZaamoInstruction<Reg>
where Reg: Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64ZabhaInstruction<Reg>
where Reg: Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64ZacasInstruction<Reg>
where Reg: Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64ZalasrInstruction<Reg>
where Reg: Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64ZalrscInstruction<Reg>
where Reg: Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64ZbaInstruction<Reg>
where Reg: Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64ZbbInstruction<Reg>
where Reg: Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64ZbcInstruction<Reg>
where Reg: Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64ZbkbInstruction<Reg>
where Reg: Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64ZbkcInstruction<Reg>
where Reg: Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64ZbkxInstruction<Reg>
where Reg: Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64ZbsInstruction<Reg>
where Reg: Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64ZcaInstruction<Reg>
where Reg: Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64ZcbInstruction<Reg>
where Reg: Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64ZcmpInstruction<Reg>
where Reg: ZcmpRegister<Type = u64> + Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64ZknInstruction<Reg>
where Reg: Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64ZkndInstruction<Reg>
where Reg: Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64ZkneInstruction<Reg>
where Reg: Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64ZknhInstruction<Reg>
where Reg: Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64ZmmulInstruction<Reg>
where Reg: Register<Type = u64>,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for ZawrsInstruction<Reg>
where Reg: Register,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for ZicondInstruction<Reg>
where Reg: Register,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for ZicsrInstruction<Reg>
where Reg: Register,

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impl<Reg, Env> ExecutableInstructionCsr<Env> for ZkrInstruction<Reg>
where Reg: Register + Register, Env: ZkrSeedSource,

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fn prepare_csr_read( _env: &Env, csr_index: u16, will_write: bool, raw_value: Reg::Type, output_value: &mut Reg::Type, ) -> Result<bool, CsrError>

Reads of seed are pass-through: the raw stored value already reflects the outcome of the most recent poll (see Self::prepare_csr_write()).

Per specification, only genuine read-write accesses (not e.g. csrrs/csrrc with rs1 = x0) are legal against seed; a pure read is rejected as an illegal access.

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fn prepare_csr_write( env: &mut Env, csr_index: u16, write_value: Reg::Type, output_value: &mut Reg::Type, ) -> Result<bool, CsrError>

Writes to seed ignore the write value entirely (per specification) and instead poll the entropy source once, storing the newly encoded ZkrSeedPoll to be observed by the next read

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impl<Reg, Env> ExecutableInstructionCsr<Env> for ZvbbInstruction<Reg>
where Reg: Register + Register, Env: Csrs<Reg>,

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fn prepare_csr_read( _env: &Env, csr_index: u16, _will_write: bool, raw_value: Reg::Type, output_value: &mut Reg::Type, ) -> Result<bool, CsrError>

Validate reads to vector CSRs from Zicsr instructions.

All vector CSRs are accessible from unprivileged code (U-mode). Reads are pass-through: the raw value stored in the CSR is the output value.

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fn prepare_csr_write( env: &mut Env, csr_index: u16, write_value: Reg::Type, output_value: &mut Reg::Type, ) -> Result<bool, CsrError>

Validate, sanitize, and mirror writes to vector CSRs from Zicsr instructions.

Enforces WARL semantics and vcsr mirroring:

  • vl, vtype, vlenb are read-only: writes are rejected
  • vxsat: only bit 0 is writable; mirrors into vcsr[0]
  • vxrm: only bits [1:0] are writable; mirrors into vcsr[2:1]
  • vcsr: only bits [2:0] are writable; mirrors into vxsat and vxrm
  • vstart: full XLEN write allowed (WARL, implementation may restrict range)
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impl<Reg, Env> ExecutableInstructionCsr<Env> for ZvbcInstruction<Reg>
where Reg: Register + Register, Env: Csrs<Reg>,

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fn prepare_csr_read( _env: &Env, csr_index: u16, _will_write: bool, raw_value: Reg::Type, output_value: &mut Reg::Type, ) -> Result<bool, CsrError>

Validate reads to vector CSRs from Zicsr instructions.

All vector CSRs are accessible from unprivileged code (U-mode). Reads are pass-through: the raw value stored in the CSR is the output value.

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fn prepare_csr_write( env: &mut Env, csr_index: u16, write_value: Reg::Type, output_value: &mut Reg::Type, ) -> Result<bool, CsrError>

Validate, sanitize, and mirror writes to vector CSRs from Zicsr instructions.

Enforces WARL semantics and vcsr mirroring:

  • vl, vtype, vlenb are read-only: writes are rejected
  • vxsat: only bit 0 is writable; mirrors into vcsr[0]
  • vxrm: only bits [1:0] are writable; mirrors into vcsr[2:1]
  • vcsr: only bits [2:0] are writable; mirrors into vxsat and vxrm
  • vstart: full XLEN write allowed (WARL, implementation may restrict range)
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impl<Reg, Env> ExecutableInstructionCsr<Env> for ZveXxInstruction<Reg>
where Reg: Register + Register, Env: Csrs<Reg>,

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fn prepare_csr_read( _env: &Env, csr_index: u16, _will_write: bool, raw_value: Reg::Type, output_value: &mut Reg::Type, ) -> Result<bool, CsrError>

Validate reads to vector CSRs from Zicsr instructions.

All vector CSRs are accessible from unprivileged code (U-mode). Reads are pass-through: the raw value stored in the CSR is the output value.

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fn prepare_csr_write( env: &mut Env, csr_index: u16, write_value: Reg::Type, output_value: &mut Reg::Type, ) -> Result<bool, CsrError>

Validate, sanitize, and mirror writes to vector CSRs from Zicsr instructions.

Enforces WARL semantics and vcsr mirroring:

  • vl, vtype, vlenb are read-only: writes are rejected
  • vxsat: only bit 0 is writable; mirrors into vcsr[0]
  • vxrm: only bits [1:0] are writable; mirrors into vcsr[2:1]
  • vcsr: only bits [2:0] are writable; mirrors into vxsat and vxrm
  • vstart: full XLEN write allowed (WARL, implementation may restrict range)
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impl<Reg, Env> ExecutableInstructionCsr<Env> for ZvkbInstruction<Reg>
where Reg: Register + Register, Env: Csrs<Reg>,

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fn prepare_csr_read( _env: &Env, csr_index: u16, _will_write: bool, raw_value: Reg::Type, output_value: &mut Reg::Type, ) -> Result<bool, CsrError>

Validate reads to vector CSRs from Zicsr instructions.

All vector CSRs are accessible from unprivileged code (U-mode). Reads are pass-through: the raw value stored in the CSR is the output value.

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fn prepare_csr_write( env: &mut Env, csr_index: u16, write_value: Reg::Type, output_value: &mut Reg::Type, ) -> Result<bool, CsrError>

Validate, sanitize, and mirror writes to vector CSRs from Zicsr instructions.

Enforces WARL semantics and vcsr mirroring:

  • vl, vtype, vlenb are read-only: writes are rejected
  • vxsat: only bit 0 is writable; mirrors into vcsr[0]
  • vxrm: only bits [1:0] are writable; mirrors into vcsr[2:1]
  • vcsr: only bits [2:0] are writable; mirrors into vxsat and vxrm
  • vstart: full XLEN write allowed (WARL, implementation may restrict range)

Implementors§