Type Alias ContractInstruction 

pub type ContractInstruction = ContractInstructionPrototype<ContractRegister>;

An instruction type used by contracts

Aliased Type

pub enum ContractInstruction {
    Ld {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        imm: i16,
    },
    Sd {
        rs2: Reg<u64>,
        rs1: Reg<u64>,
        imm: i16,
    },
    Add {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Addi {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        imm: i16,
    },
    Xor {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Rori {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        shamt: u8,
    },
    Srli {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        shamt: u8,
    },
    Or {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    And {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Slli {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        shamt: u8,
    },
    Lbu {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        imm: i16,
    },
    Auipc {
        rd: Reg<u64>,
        imm: i32,
    },
    Jalr {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        imm: i16,
    },
    Sb {
        rs2: Reg<u64>,
        rs1: Reg<u64>,
        imm: i16,
    },
    Roriw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        shamt: u8,
    },
    Sub {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Sltu {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Mulhu {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Mul {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Sh1add {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    CAddi4spn {
        rd: Reg<u64>,
        nzuimm: u16,
    },
    CLw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        uimm: u8,
    },
    CLd {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        uimm: u8,
    },
    CSw {
        rs1: Reg<u64>,
        rs2: Reg<u64>,
        uimm: u8,
    },
    CSd {
        rs1: Reg<u64>,
        rs2: Reg<u64>,
        uimm: u8,
    },
    CNop,
    CAddi {
        rd: Reg<u64>,
        nzimm: i8,
    },
    CAddiw {
        rd: Reg<u64>,
        imm: i8,
    },
    CLi {
        rd: Reg<u64>,
        imm: i8,
    },
    CAddi16sp {
        nzimm: i16,
    },
    CLui {
        rd: Reg<u64>,
        nzimm: i32,
    },
    CSrli {
        rd: Reg<u64>,
        shamt: u8,
    },
    CSrai {
        rd: Reg<u64>,
        shamt: u8,
    },
    CAndi {
        rd: Reg<u64>,
        imm: i8,
    },
    CSub {
        rd: Reg<u64>,
        rs2: Reg<u64>,
    },
    CXor {
        rd: Reg<u64>,
        rs2: Reg<u64>,
    },
    COr {
        rd: Reg<u64>,
        rs2: Reg<u64>,
    },
    CAnd {
        rd: Reg<u64>,
        rs2: Reg<u64>,
    },
    CSubw {
        rd: Reg<u64>,
        rs2: Reg<u64>,
    },
    CAddw {
        rd: Reg<u64>,
        rs2: Reg<u64>,
    },
    CJ {
        imm: i16,
    },
    CBeqz {
        rs1: Reg<u64>,
        imm: i16,
    },
    CBnez {
        rs1: Reg<u64>,
        imm: i16,
    },
    CSlli {
        rd: Reg<u64>,
        shamt: u8,
    },
    CLwsp {
        rd: Reg<u64>,
        uimm: u8,
    },
    CLdsp {
        rd: Reg<u64>,
        uimm: u16,
    },
    CJr {
        rs1: Reg<u64>,
    },
    CMv {
        rd: Reg<u64>,
        rs2: Reg<u64>,
    },
    CEbreak,
    CJalr {
        rs1: Reg<u64>,
    },
    CAdd {
        rd: Reg<u64>,
        rs2: Reg<u64>,
    },
    CSwsp {
        rs2: Reg<u64>,
        uimm: u8,
    },
    CSdsp {
        rs2: Reg<u64>,
        uimm: u16,
    },
    CUnimp,
    CLbu {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        uimm: u8,
    },
    CLh {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        uimm: u8,
    },
    CLhu {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        uimm: u8,
    },
    CSb {
        rs1: Reg<u64>,
        rs2: Reg<u64>,
        uimm: u8,
    },
    CSh {
        rs1: Reg<u64>,
        rs2: Reg<u64>,
        uimm: u8,
    },
    CZextB {
        rd: Reg<u64>,
    },
    CSextB {
        rd: Reg<u64>,
    },
    CZextH {
        rd: Reg<u64>,
    },
    CSextH {
        rd: Reg<u64>,
    },
    CZextW {
        rd: Reg<u64>,
    },
    CNot {
        rd: Reg<u64>,
    },
    CMul {
        rd: Reg<u64>,
        rs2: Reg<u64>,
    },
    CmPush {
        urlist: ZcmpUrlist<Reg<u64>>,
        stack_adj: u32,
    },
    CmPop {
        urlist: ZcmpUrlist<Reg<u64>>,
        stack_adj: u32,
    },
    CmPopretz {
        urlist: ZcmpUrlist<Reg<u64>>,
        stack_adj: u32,
    },
    CmPopret {
        urlist: ZcmpUrlist<Reg<u64>>,
        stack_adj: u32,
    },
    CmMva01s {
        r1s: Reg<u64>,
        r2s: Reg<u64>,
    },
    CmMvsa01 {
        r1s: Reg<u64>,
        r2s: Reg<u64>,
    },
    Sll {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Slt {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Srl {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Sra {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Addw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Subw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Sllw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Srlw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Sraw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Slti {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        imm: i16,
    },
    Sltiu {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        imm: i16,
    },
    Xori {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        imm: i16,
    },
    Ori {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        imm: i16,
    },
    Andi {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        imm: i16,
    },
    Srai {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        shamt: u8,
    },
    Addiw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        imm: i16,
    },
    Slliw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        shamt: u8,
    },
    Srliw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        shamt: u8,
    },
    Sraiw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        shamt: u8,
    },
    Lb {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        imm: i16,
    },
    Lh {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        imm: i16,
    },
    Lw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        imm: i16,
    },
    Lhu {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        imm: i16,
    },
    Lwu {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        imm: i16,
    },
    Sh {
        rs2: Reg<u64>,
        rs1: Reg<u64>,
        imm: i16,
    },
    Sw {
        rs2: Reg<u64>,
        rs1: Reg<u64>,
        imm: i16,
    },
    Beq {
        rs1: Reg<u64>,
        rs2: Reg<u64>,
        imm: i32,
    },
    Bne {
        rs1: Reg<u64>,
        rs2: Reg<u64>,
        imm: i32,
    },
    Blt {
        rs1: Reg<u64>,
        rs2: Reg<u64>,
        imm: i32,
    },
    Bge {
        rs1: Reg<u64>,
        rs2: Reg<u64>,
        imm: i32,
    },
    Bltu {
        rs1: Reg<u64>,
        rs2: Reg<u64>,
        imm: i32,
    },
    Bgeu {
        rs1: Reg<u64>,
        rs2: Reg<u64>,
        imm: i32,
    },
    Lui {
        rd: Reg<u64>,
        imm: i32,
    },
    Jal {
        rd: Reg<u64>,
        imm: i32,
    },
    FenceTso,
    Ebreak,
    Unimp,
    Mulh {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Mulhsu {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Div {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Divu {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Rem {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Remu {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Mulw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Divw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Divuw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Remw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Remuw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    AddUw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Sh1addUw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Sh2add {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Sh2addUw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Sh3add {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Sh3addUw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    SlliUw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        shamt: u8,
    },
    Andn {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Orn {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Xnor {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Clz {
        rd: Reg<u64>,
        rs1: Reg<u64>,
    },
    Clzw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
    },
    Ctz {
        rd: Reg<u64>,
        rs1: Reg<u64>,
    },
    Ctzw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
    },
    Cpop {
        rd: Reg<u64>,
        rs1: Reg<u64>,
    },
    Cpopw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
    },
    Max {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Maxu {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Min {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Minu {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Sextb {
        rd: Reg<u64>,
        rs1: Reg<u64>,
    },
    Sexth {
        rd: Reg<u64>,
        rs1: Reg<u64>,
    },
    Zexth {
        rd: Reg<u64>,
        rs1: Reg<u64>,
    },
    Rol {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Rolw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Ror {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Rorw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Orcb {
        rd: Reg<u64>,
        rs1: Reg<u64>,
    },
    Rev8 {
        rd: Reg<u64>,
        rs1: Reg<u64>,
    },
    Bset {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Bseti {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        shamt: u8,
    },
    Bclr {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Bclri {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        shamt: u8,
    },
    Binv {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Binvi {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        shamt: u8,
    },
    Bext {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Bexti {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        shamt: u8,
    },
    Clmul {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Clmulh {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Clmulr {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Pack {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Packh {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Packw {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Brev8 {
        rd: Reg<u64>,
        rs1: Reg<u64>,
    },
    Xperm4 {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Xperm8 {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Aes64Ds {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Aes64Dsm {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Aes64Im {
        rd: Reg<u64>,
        rs1: Reg<u64>,
    },
    Aes64Ks1i {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rnum: Rv64ZkndKsRnum,
    },
    Aes64Ks2 {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Aes64Es {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Aes64Esm {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    Sha256Sig0 {
        rd: Reg<u64>,
        rs1: Reg<u64>,
    },
    Sha256Sig1 {
        rd: Reg<u64>,
        rs1: Reg<u64>,
    },
    Sha256Sum0 {
        rd: Reg<u64>,
        rs1: Reg<u64>,
    },
    Sha256Sum1 {
        rd: Reg<u64>,
        rs1: Reg<u64>,
    },
    Sha512Sig0 {
        rd: Reg<u64>,
        rs1: Reg<u64>,
    },
    Sha512Sig1 {
        rd: Reg<u64>,
        rs1: Reg<u64>,
    },
    Sha512Sum0 {
        rd: Reg<u64>,
        rs1: Reg<u64>,
    },
    Sha512Sum1 {
        rd: Reg<u64>,
        rs1: Reg<u64>,
    },
    CzeroEqz {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
    CzeroNez {
        rd: Reg<u64>,
        rs1: Reg<u64>,
        rs2: Reg<u64>,
    },
}

Variants

Ld

Fields

rd: Reg<u64>

rs1: Reg<u64>

imm: i16

Sd

Fields

rs2: Reg<u64>

rs1: Reg<u64>

imm: i16

Add

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Addi

Fields

rd: Reg<u64>

rs1: Reg<u64>

imm: i16

Xor

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Rori

Fields

rd: Reg<u64>

rs1: Reg<u64>

shamt: u8

Srli

Fields

rd: Reg<u64>

rs1: Reg<u64>

shamt: u8

Or

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

And

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Slli

Fields

rd: Reg<u64>

rs1: Reg<u64>

shamt: u8

Lbu

Fields

rd: Reg<u64>

rs1: Reg<u64>

imm: i16

Auipc

Fields

rd: Reg<u64>

imm: i32

Jalr

Fields

rd: Reg<u64>

rs1: Reg<u64>

imm: i16

Sb

Fields

rs2: Reg<u64>

rs1: Reg<u64>

imm: i16

Roriw

Fields

rd: Reg<u64>

rs1: Reg<u64>

shamt: u8

Sub

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Sltu

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Mulhu

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Mul

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Sh1add

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

CAddi4spn

C.ADDI4SPN rd’ = sp + nzuimm (nzuimm ∈ 4..1020 step 4)

Fields

rd: Reg<u64>

nzuimm: u16

CLw

C.LW rd’ = sext(mem32[rs1’ + uimm])

Fields

rd: Reg<u64>

rs1: Reg<u64>

uimm: u8

CLd

C.LD rd’ = mem64[rs1’ + uimm]

Fields

rd: Reg<u64>

rs1: Reg<u64>

uimm: u8

CSw

C.SW mem32[rs1’ + uimm] = rs2’

Fields

rs1: Reg<u64>

rs2: Reg<u64>

uimm: u8

CSd

C.SD mem64[rs1’ + uimm] = rs2’

Fields

rs1: Reg<u64>

rs2: Reg<u64>

uimm: u8

CNop

C.NOP (ADDI x0, x0, 0 with rd==x0 and nzimm==0)

CAddi

C.ADDI rd += nzimm (rd != x0)

Fields

rd: Reg<u64>

nzimm: i8

CAddiw

C.ADDIW rd = sext((rd[31:0] + imm)[31:0]) (rd != x0)

Fields

rd: Reg<u64>

imm: i8

CLi

C.LI rd = sext(imm) (rd=x0 is a HINT)

Fields

rd: Reg<u64>

imm: i8

CAddi16sp

C.ADDI16SP sp += nzimm*16 (nzimm != 0)

Fields

nzimm: i16

CLui

C.LUI rd = sext(nzimm << 12) (rd != x0, rd != x2, nzimm != 0)

Fields

rd: Reg<u64>

nzimm: i32

CSrli

C.SRLI rd’ >>= shamt (logical right shift; shamt=0 with rd’=x0 is a HINT)

Fields

rd: Reg<u64>

shamt: u8

CSrai

C.SRAI rd’ >>= shamt (arithmetic right shift; shamt=0 with rd’=x0 is a HINT)

Fields

rd: Reg<u64>

shamt: u8

CAndi

C.ANDI rd’ &= sext(imm)

Fields

rd: Reg<u64>

imm: i8

CSub

C.SUB rd’ -= rs2’

Fields

rd: Reg<u64>

rs2: Reg<u64>

CXor

C.XOR rd’ ^= rs2’

Fields

rd: Reg<u64>

rs2: Reg<u64>

COr

C.OR rd’ |= rs2’

Fields

rd: Reg<u64>

rs2: Reg<u64>

CAnd

C.AND rd’ &= rs2’

Fields

rd: Reg<u64>

rs2: Reg<u64>

CSubw

C.SUBW rd’ = sext((rd’[31:0] - rs2’[31:0])[31:0])

Fields

rd: Reg<u64>

rs2: Reg<u64>

CAddw

C.ADDW rd’ = sext((rd’[31:0] + rs2’[31:0])[31:0])

Fields

rd: Reg<u64>

rs2: Reg<u64>

CJ

C.J pc += sext(imm)

Fields

imm: i16

CBeqz

C.BEQZ if rs1’ == 0: pc += sext(imm)

Fields

rs1: Reg<u64>

imm: i16

CBnez

C.BNEZ if rs1’ != 0: pc += sext(imm)

Fields

rs1: Reg<u64>

imm: i16

CSlli

C.SLLI rd <<= shamt (rd=x0 or shamt=0 is a HINT)

Fields

rd: Reg<u64>

shamt: u8

CLwsp

C.LWSP rd = sext(mem32[sp + uimm]) (rd != x0)

Fields

rd: Reg<u64>

uimm: u8

CLdsp

C.LDSP rd = mem64[sp + uimm] (rd != x0)

Fields

rd: Reg<u64>

uimm: u16

CJr

C.JR pc = rs1 (rs1 != x0)

Fields

rs1: Reg<u64>

CMv

C.MV rd = rs2 (rs2 != x0; rd=x0 is a HINT)

Fields

rd: Reg<u64>

rs2: Reg<u64>

CEbreak

C.EBREAK

CJalr

C.JALR ra = pc+2; pc = rs1 (rs1 != x0)

Fields

rs1: Reg<u64>

CAdd

C.ADD rd += rs2 (rs2 != x0; rd=x0 is a HINT)

Fields

rd: Reg<u64>

rs2: Reg<u64>

CSwsp

C.SWSP mem32[sp + uimm] = rs2

Fields

rs2: Reg<u64>

uimm: u8

CSdsp

C.SDSP mem64[sp + uimm] = rs2

Fields

rs2: Reg<u64>

uimm: u16

CUnimp

CLbu

C.LBU rd’ = zero_extend(mem8[rs1’ + uimm]) uimm ∈ {0,1,2,3}

Fields

rd: Reg<u64>

rs1: Reg<u64>

uimm: u8

CLh

C.LH rd’ = sign_extend(mem16[rs1’ + uimm]) uimm ∈ {0,2}

Fields

rd: Reg<u64>

rs1: Reg<u64>

uimm: u8

CLhu

C.LHU rd’ = zero_extend(mem16[rs1’ + uimm]) uimm ∈ {0,2}

Fields

rd: Reg<u64>

rs1: Reg<u64>

uimm: u8

CSb

C.SB mem8[rs1’ + uimm] = rs2’ uimm ∈ {0,1,2,3}

Fields

rs1: Reg<u64>

rs2: Reg<u64>

uimm: u8

CSh

C.SH mem16[rs1’ + uimm] = rs2’ uimm ∈ {0,2}

Fields

rs1: Reg<u64>

rs2: Reg<u64>

uimm: u8

CZextB

C.ZEXT.B rd’ = rd’ & 0xff

Fields

rd: Reg<u64>

CSextB

C.SEXT.B rd’ = sext(rd’[7:0]) (requires Zbb)

Fields

rd: Reg<u64>

CZextH

C.ZEXT.H rd’ = rd’ & 0xffff (requires Zbb)

Fields

rd: Reg<u64>

CSextH

C.SEXT.H rd’ = sext(rd’[15:0]) (requires Zbb)

Fields

rd: Reg<u64>

CZextW

C.ZEXT.W rd’ = rd’ & 0xffff_ffff (requires Zba)

Fields

rd: Reg<u64>

CNot

C.NOT rd’ = ~rd’

Fields

rd: Reg<u64>

CMul

C.MUL rd’ = (rd’ * rs2’)[XLEN-1:0] (requires M or Zmmul)

Fields

rd: Reg<u64>

rs2: Reg<u64>

CmPush

CM.PUSH - push reg_list, decrement sp by stack_adj

stack_adj = urlist.stack_adj_base() + spimm * 16 from the encoding.

Fields

urlist: ZcmpUrlist<Reg<u64>>

stack_adj: u32

CmPop

CM.POP - pop reg_list, increment sp by stack_adj (no return)

Fields

urlist: ZcmpUrlist<Reg<u64>>

stack_adj: u32

CmPopretz

CM.POPRETZ - pop reg_list, set a0=0, increment sp, return

Fields

urlist: ZcmpUrlist<Reg<u64>>

stack_adj: u32

CmPopret

CM.POPRET - pop reg_list, increment sp, return

Fields

urlist: ZcmpUrlist<Reg<u64>>

stack_adj: u32

CmMva01s

CM.MVA01S - a0 = r1s’, a1 = r2s’

Fields

r1s: Reg<u64>

r2s: Reg<u64>

CmMvsa01

CM.MVSA01 - r1s’ = a0, r2s’ = a1 (r1s’ != r2s’)

Fields

r1s: Reg<u64>

r2s: Reg<u64>

Sll

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Slt

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Srl

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Sra

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Addw

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Subw

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Sllw

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Srlw

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Sraw

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Slti

Fields

rd: Reg<u64>

rs1: Reg<u64>

imm: i16

Sltiu

Fields

rd: Reg<u64>

rs1: Reg<u64>

imm: i16

Xori

Fields

rd: Reg<u64>

rs1: Reg<u64>

imm: i16

Ori

Fields

rd: Reg<u64>

rs1: Reg<u64>

imm: i16

Andi

Fields

rd: Reg<u64>

rs1: Reg<u64>

imm: i16

Srai

Fields

rd: Reg<u64>

rs1: Reg<u64>

shamt: u8

Addiw

Fields

rd: Reg<u64>

rs1: Reg<u64>

imm: i16

Slliw

Fields

rd: Reg<u64>

rs1: Reg<u64>

shamt: u8

Srliw

Fields

rd: Reg<u64>

rs1: Reg<u64>

shamt: u8

Sraiw

Fields

rd: Reg<u64>

rs1: Reg<u64>

shamt: u8

Lb

Fields

rd: Reg<u64>

rs1: Reg<u64>

imm: i16

Lh

Fields

rd: Reg<u64>

rs1: Reg<u64>

imm: i16

Lw

Fields

rd: Reg<u64>

rs1: Reg<u64>

imm: i16

Lhu

Fields

rd: Reg<u64>

rs1: Reg<u64>

imm: i16

Lwu

Fields

rd: Reg<u64>

rs1: Reg<u64>

imm: i16

Sh

Fields

rs2: Reg<u64>

rs1: Reg<u64>

imm: i16

Sw

Fields

rs2: Reg<u64>

rs1: Reg<u64>

imm: i16

Beq

Fields

rs1: Reg<u64>

rs2: Reg<u64>

imm: i32

Bne

Fields

rs1: Reg<u64>

rs2: Reg<u64>

imm: i32

Blt

Fields

rs1: Reg<u64>

rs2: Reg<u64>

imm: i32

Bge

Fields

rs1: Reg<u64>

rs2: Reg<u64>

imm: i32

Bltu

Fields

rs1: Reg<u64>

rs2: Reg<u64>

imm: i32

Bgeu

Fields

rs1: Reg<u64>

rs2: Reg<u64>

imm: i32

Lui

Fields

rd: Reg<u64>

imm: i32

Jal

Fields

rd: Reg<u64>

imm: i32

FenceTso

Ebreak

Unimp

Mulh

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Mulhsu

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Div

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Divu

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Rem

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Remu

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Mulw

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Divw

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Divuw

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Remw

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Remuw

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

AddUw

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Sh1addUw

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Sh2add

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Sh2addUw

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Sh3add

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Sh3addUw

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

SlliUw

Fields

rd: Reg<u64>

rs1: Reg<u64>

shamt: u8

Andn

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Orn

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Xnor

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Clz

Fields

rd: Reg<u64>

rs1: Reg<u64>

Clzw

Fields

rd: Reg<u64>

rs1: Reg<u64>

Ctz

Fields

rd: Reg<u64>

rs1: Reg<u64>

Ctzw

Fields

rd: Reg<u64>

rs1: Reg<u64>

Cpop

Fields

rd: Reg<u64>

rs1: Reg<u64>

Cpopw

Fields

rd: Reg<u64>

rs1: Reg<u64>

Max

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Maxu

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Min

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Minu

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Sextb

Fields

rd: Reg<u64>

rs1: Reg<u64>

Sexth

Fields

rd: Reg<u64>

rs1: Reg<u64>

Zexth

Fields

rd: Reg<u64>

rs1: Reg<u64>

Rol

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Rolw

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Ror

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Rorw

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Orcb

Fields

rd: Reg<u64>

rs1: Reg<u64>

Rev8

Fields

rd: Reg<u64>

rs1: Reg<u64>

Bset

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Bseti

Fields

rd: Reg<u64>

rs1: Reg<u64>

shamt: u8

Bclr

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Bclri

Fields

rd: Reg<u64>

rs1: Reg<u64>

shamt: u8

Binv

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Binvi

Fields

rd: Reg<u64>

rs1: Reg<u64>

shamt: u8

Bext

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Bexti

Fields

rd: Reg<u64>

rs1: Reg<u64>

shamt: u8

Clmul

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Clmulh

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Clmulr

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Pack

Pack low 32 bits of rs1 and rs2 into rd

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Packh

Pack low 8 bits of rs1 and rs2 into rd bytes 0 and 1

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Packw

Pack low 16 bits of rs1 and rs2 into lower 32 bits of rd, sign-extend

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Brev8

Reverse bits in each byte of rs1

Fields

rd: Reg<u64>

rs1: Reg<u64>

Xperm4

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Xperm8

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Aes64Ds

AES final round decryption: InvShiftRows + InvSubBytes, no MixColumns

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Aes64Dsm

AES middle round decryption: InvShiftRows + InvSubBytes + InvMixColumns

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Aes64Im

AES inverse MixColumns on each 32-bit word of rs1

Fields

rd: Reg<u64>

rs1: Reg<u64>

Aes64Ks1i

AES key schedule step 1 (rnum in 0..=10)

Fields

rd: Reg<u64>

rs1: Reg<u64>

rnum: Rv64ZkndKsRnum

Aes64Ks2

AES key schedule step 2

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Aes64Es

AES final round encryption: ShiftRows + SubBytes, no MixColumns

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Aes64Esm

AES middle round encryption: ShiftRows + SubBytes + MixColumns

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

Sha256Sig0

Fields

rd: Reg<u64>

rs1: Reg<u64>

Sha256Sig1

Fields

rd: Reg<u64>

rs1: Reg<u64>

Sha256Sum0

Fields

rd: Reg<u64>

rs1: Reg<u64>

Sha256Sum1

Fields

rd: Reg<u64>

rs1: Reg<u64>

Sha512Sig0

Fields

rd: Reg<u64>

rs1: Reg<u64>

Sha512Sig1

Fields

rd: Reg<u64>

rs1: Reg<u64>

Sha512Sum0

Fields

rd: Reg<u64>

rs1: Reg<u64>

Sha512Sum1

Fields

rd: Reg<u64>

rs1: Reg<u64>

CzeroEqz

czero.eqz rd, rs1, rs2 - move zero to rd if rs2 == 0, else move rs1

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>

CzeroNez

czero.nez rd, rs1, rs2 - move zero to rd if rs2 != 0, else move rs1

Fields

rd: Reg<u64>

rs1: Reg<u64>

rs2: Reg<u64>