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ContractInstructionPrototype

ab_contract_file::contract_instruction_prototype

Enum ContractInstructionPrototype 

Source 
pub enum ContractInstructionPrototype<Reg> {

Show 183 variants    Ld {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Sd {
        rs2: Reg,
        rs1: Reg,
        imm: i16,
    },
    Add {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Addi {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Xor {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Rori {
        rd: Reg,
        rs1: Reg,
        shamt: u8,
    },
    Srli {
        rd: Reg,
        rs1: Reg,
        shamt: u8,
    },
    Or {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    And {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Slli {
        rd: Reg,
        rs1: Reg,
        shamt: u8,
    },
    Lbu {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Auipc {
        rd: Reg,
        imm: i32,
    },
    Jalr {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Sb {
        rs2: Reg,
        rs1: Reg,
        imm: i16,
    },
    Roriw {
        rd: Reg,
        rs1: Reg,
        shamt: u8,
    },
    Sub {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sltu {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Mulhu {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Mul {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sh1add {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    CAddi4spn {
        rd: Reg,
        nzuimm: u16,
    },
    CLw {
        rd: Reg,
        rs1: Reg,
        uimm: u8,
    },
    CLd {
        rd: Reg,
        rs1: Reg,
        uimm: u8,
    },
    CSw {
        rs1: Reg,
        rs2: Reg,
        uimm: u8,
    },
    CSd {
        rs1: Reg,
        rs2: Reg,
        uimm: u8,
    },
    CNop,
    CAddi {
        rd: Reg,
        nzimm: i8,
    },
    CAddiw {
        rd: Reg,
        imm: i8,
    },
    CLi {
        rd: Reg,
        imm: i8,
    },
    CAddi16sp {
        nzimm: i16,
    },
    CLui {
        rd: Reg,
        nzimm: i32,
    },
    CSrli {
        rd: Reg,
        shamt: u8,
    },
    CSrai {
        rd: Reg,
        shamt: u8,
    },
    CAndi {
        rd: Reg,
        imm: i8,
    },
    CSub {
        rd: Reg,
        rs2: Reg,
    },
    CXor {
        rd: Reg,
        rs2: Reg,
    },
    COr {
        rd: Reg,
        rs2: Reg,
    },
    CAnd {
        rd: Reg,
        rs2: Reg,
    },
    CSubw {
        rd: Reg,
        rs2: Reg,
    },
    CAddw {
        rd: Reg,
        rs2: Reg,
    },
    CJ {
        imm: i16,
    },
    CBeqz {
        rs1: Reg,
        imm: i16,
    },
    CBnez {
        rs1: Reg,
        imm: i16,
    },
    CSlli {
        rd: Reg,
        shamt: u8,
    },
    CLwsp {
        rd: Reg,
        uimm: u8,
    },
    CLdsp {
        rd: Reg,
        uimm: u16,
    },
    CJr {
        rs1: Reg,
    },
    CMv {
        rd: Reg,
        rs2: Reg,
    },
    CEbreak,
    CJalr {
        rs1: Reg,
    },
    CAdd {
        rd: Reg,
        rs2: Reg,
    },
    CSwsp {
        rs2: Reg,
        uimm: u8,
    },
    CSdsp {
        rs2: Reg,
        uimm: u16,
    },
    CUnimp,
    CLbu {
        rd: Reg,
        rs1: Reg,
        uimm: u8,
    },
    CLh {
        rd: Reg,
        rs1: Reg,
        uimm: u8,
    },
    CLhu {
        rd: Reg,
        rs1: Reg,
        uimm: u8,
    },
    CSb {
        rs1: Reg,
        rs2: Reg,
        uimm: u8,
    },
    CSh {
        rs1: Reg,
        rs2: Reg,
        uimm: u8,
    },
    CZextB {
        rd: Reg,
    },
    CSextB {
        rd: Reg,
    },
    CZextH {
        rd: Reg,
    },
    CSextH {
        rd: Reg,
    },
    CZextW {
        rd: Reg,
    },
    CNot {
        rd: Reg,
    },
    CMul {
        rd: Reg,
        rs2: Reg,
    },
    CmPush {
        urlist: ZcmpUrlist<Reg>,
        stack_adj: u32,
    },
    CmPop {
        urlist: ZcmpUrlist<Reg>,
        stack_adj: u32,
    },
    CmPopretz {
        urlist: ZcmpUrlist<Reg>,
        stack_adj: u32,
    },
    CmPopret {
        urlist: ZcmpUrlist<Reg>,
        stack_adj: u32,
    },
    CmMva01s {
        r1s: Reg,
        r2s: Reg,
    },
    CmMvsa01 {
        r1s: Reg,
        r2s: Reg,
    },
    Sll {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Slt {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Srl {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sra {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Addw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Subw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sllw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Srlw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sraw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Slti {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Sltiu {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Xori {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Ori {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Andi {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Srai {
        rd: Reg,
        rs1: Reg,
        shamt: u8,
    },
    Addiw {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Slliw {
        rd: Reg,
        rs1: Reg,
        shamt: u8,
    },
    Srliw {
        rd: Reg,
        rs1: Reg,
        shamt: u8,
    },
    Sraiw {
        rd: Reg,
        rs1: Reg,
        shamt: u8,
    },
    Lb {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Lh {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Lw {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Lhu {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Lwu {
        rd: Reg,
        rs1: Reg,
        imm: i16,
    },
    Sh {
        rs2: Reg,
        rs1: Reg,
        imm: i16,
    },
    Sw {
        rs2: Reg,
        rs1: Reg,
        imm: i16,
    },
    Beq {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Bne {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Blt {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Bge {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Bltu {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Bgeu {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Lui {
        rd: Reg,
        imm: i32,
    },
    Jal {
        rd: Reg,
        imm: i32,
    },
    FenceTso,
    Ebreak,
    Unimp,
    Mulh {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Mulhsu {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Div {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Divu {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Rem {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Remu {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Mulw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Divw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Divuw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Remw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Remuw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    AddUw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sh1addUw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sh2add {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sh2addUw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sh3add {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sh3addUw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    SlliUw {
        rd: Reg,
        rs1: Reg,
        shamt: u8,
    },
    Andn {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Orn {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Xnor {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Clz {
        rd: Reg,
        rs1: Reg,
    },
    Clzw {
        rd: Reg,
        rs1: Reg,
    },
    Ctz {
        rd: Reg,
        rs1: Reg,
    },
    Ctzw {
        rd: Reg,
        rs1: Reg,
    },
    Cpop {
        rd: Reg,
        rs1: Reg,
    },
    Cpopw {
        rd: Reg,
        rs1: Reg,
    },
    Max {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Maxu {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Min {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Minu {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sextb {
        rd: Reg,
        rs1: Reg,
    },
    Sexth {
        rd: Reg,
        rs1: Reg,
    },
    Zexth {
        rd: Reg,
        rs1: Reg,
    },
    Rol {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Rolw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Ror {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Rorw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Orcb {
        rd: Reg,
        rs1: Reg,
    },
    Rev8 {
        rd: Reg,
        rs1: Reg,
    },
    Bset {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Bseti {
        rd: Reg,
        rs1: Reg,
        shamt: u8,
    },
    Bclr {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Bclri {
        rd: Reg,
        rs1: Reg,
        shamt: u8,
    },
    Binv {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Binvi {
        rd: Reg,
        rs1: Reg,
        shamt: u8,
    },
    Bext {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Bexti {
        rd: Reg,
        rs1: Reg,
        shamt: u8,
    },
    Clmul {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Clmulh {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Clmulr {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Pack {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Packh {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Packw {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Brev8 {
        rd: Reg,
        rs1: Reg,
    },
    Xperm4 {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Xperm8 {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Aes64Ds {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Aes64Dsm {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Aes64Im {
        rd: Reg,
        rs1: Reg,
    },
    Aes64Ks1i {
        rd: Reg,
        rs1: Reg,
        rnum: Rv64ZkndKsRnum,
    },
    Aes64Ks2 {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Aes64Es {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Aes64Esm {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sha256Sig0 {
        rd: Reg,
        rs1: Reg,
    },
    Sha256Sig1 {
        rd: Reg,
        rs1: Reg,
    },
    Sha256Sum0 {
        rd: Reg,
        rs1: Reg,
    },
    Sha256Sum1 {
        rd: Reg,
        rs1: Reg,
    },
    Sha512Sig0 {
        rd: Reg,
        rs1: Reg,
    },
    Sha512Sig1 {
        rd: Reg,
        rs1: Reg,
    },
    Sha512Sum0 {
        rd: Reg,
        rs1: Reg,
    },
    Sha512Sum1 {
        rd: Reg,
        rs1: Reg,
    },
    CzeroEqz {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    CzeroNez {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },

}
Expand description

An instruction type used by contracts

Variants§

§

Ld

Fields

§rd: Reg
§rs1: Reg
§imm: i16
§

Sd

Fields

§rs2: Reg
§rs1: Reg
§imm: i16
§

Add

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Addi

Fields

§rd: Reg
§rs1: Reg
§imm: i16
§

Xor

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Rori

Fields

§rd: Reg
§rs1: Reg
§shamt: u8
§

Srli

Fields

§rd: Reg
§rs1: Reg
§shamt: u8
§

Or

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

And

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Slli

Fields

§rd: Reg
§rs1: Reg
§shamt: u8
§

Lbu

Fields

§rd: Reg
§rs1: Reg
§imm: i16
§

Auipc

Fields

§rd: Reg
§imm: i32
§

Jalr

Fields

§rd: Reg
§rs1: Reg
§imm: i16
§

Sb

Fields

§rs2: Reg
§rs1: Reg
§imm: i16
§

Roriw

Fields

§rd: Reg
§rs1: Reg
§shamt: u8
§

Sub

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Sltu

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Mulhu

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Mul

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Sh1add

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

CAddi4spn

C.ADDI4SPN rd’ = sp + nzuimm (nzuimm ∈ 4..1020 step 4)

Fields

§rd: Reg
§nzuimm: u16
§

CLw

C.LW rd’ = sext(mem32[rs1’ + uimm])

Fields

§rd: Reg
§rs1: Reg
§uimm: u8
§

CLd

C.LD rd’ = mem64[rs1’ + uimm]

Fields

§rd: Reg
§rs1: Reg
§uimm: u8
§

CSw

C.SW mem32[rs1’ + uimm] = rs2’

Fields

§rs1: Reg
§rs2: Reg
§uimm: u8
§

CSd

C.SD mem64[rs1’ + uimm] = rs2’

Fields

§rs1: Reg
§rs2: Reg
§uimm: u8
§

CNop

C.NOP (ADDI x0, x0, 0 with rd==x0 and nzimm==0)

§

CAddi

C.ADDI rd += nzimm (rd != x0)

Fields

§rd: Reg
§nzimm: i8
§

CAddiw

C.ADDIW rd = sext((rd[31:0] + imm)[31:0]) (rd != x0)

Fields

§rd: Reg
§imm: i8
§

CLi

C.LI rd = sext(imm) (rd=x0 is a HINT)

Fields

§rd: Reg
§imm: i8
§

CAddi16sp

C.ADDI16SP sp += nzimm*16 (nzimm != 0)

Fields

§nzimm: i16
§

CLui

C.LUI rd = sext(nzimm << 12) (rd != x0, rd != x2, nzimm != 0)

Fields

§rd: Reg
§nzimm: i32
§

CSrli

C.SRLI rd’ >>= shamt (logical right shift; shamt=0 with rd’=x0 is a HINT)

Fields

§rd: Reg
§shamt: u8
§

CSrai

C.SRAI rd’ >>= shamt (arithmetic right shift; shamt=0 with rd’=x0 is a HINT)

Fields

§rd: Reg
§shamt: u8
§

CAndi

C.ANDI rd’ &= sext(imm)

Fields

§rd: Reg
§imm: i8
§

CSub

C.SUB rd’ -= rs2’

Fields

§rd: Reg
§rs2: Reg
§

CXor

C.XOR rd’ ^= rs2’

Fields

§rd: Reg
§rs2: Reg
§

COr

C.OR rd’ |= rs2’

Fields

§rd: Reg
§rs2: Reg
§

CAnd

C.AND rd’ &= rs2’

Fields

§rd: Reg
§rs2: Reg
§

CSubw

C.SUBW rd’ = sext((rd’[31:0] - rs2’[31:0])[31:0])

Fields

§rd: Reg
§rs2: Reg
§

CAddw

C.ADDW rd’ = sext((rd’[31:0] + rs2’[31:0])[31:0])

Fields

§rd: Reg
§rs2: Reg
§

CJ

C.J pc += sext(imm)

Fields

§imm: i16
§

CBeqz

C.BEQZ if rs1’ == 0: pc += sext(imm)

Fields

§rs1: Reg
§imm: i16
§

CBnez

C.BNEZ if rs1’ != 0: pc += sext(imm)

Fields

§rs1: Reg
§imm: i16
§

CSlli

C.SLLI rd <<= shamt (rd=x0 or shamt=0 is a HINT)

Fields

§rd: Reg
§shamt: u8
§

CLwsp

C.LWSP rd = sext(mem32[sp + uimm]) (rd != x0)

Fields

§rd: Reg
§uimm: u8
§

CLdsp

C.LDSP rd = mem64[sp + uimm] (rd != x0)

Fields

§rd: Reg
§uimm: u16
§

CJr

C.JR pc = rs1 (rs1 != x0)

Fields

§rs1: Reg
§

CMv

C.MV rd = rs2 (rs2 != x0; rd=x0 is a HINT)

Fields

§rd: Reg
§rs2: Reg
§

CEbreak

C.EBREAK

§

CJalr

C.JALR ra = pc+2; pc = rs1 (rs1 != x0)

Fields

§rs1: Reg
§

CAdd

C.ADD rd += rs2 (rs2 != x0; rd=x0 is a HINT)

Fields

§rd: Reg
§rs2: Reg
§

CSwsp

C.SWSP mem32[sp + uimm] = rs2

Fields

§rs2: Reg
§uimm: u8
§

CSdsp

C.SDSP mem64[sp + uimm] = rs2

Fields

§rs2: Reg
§uimm: u16
§

CUnimp

§

CLbu

C.LBU rd’ = zero_extend(mem8[rs1’ + uimm]) uimm ∈ {0,1,2,3}

Fields

§rd: Reg
§rs1: Reg
§uimm: u8
§

CLh

C.LH rd’ = sign_extend(mem16[rs1’ + uimm]) uimm ∈ {0,2}

Fields

§rd: Reg
§rs1: Reg
§uimm: u8
§

CLhu

C.LHU rd’ = zero_extend(mem16[rs1’ + uimm]) uimm ∈ {0,2}

Fields

§rd: Reg
§rs1: Reg
§uimm: u8
§

CSb

C.SB mem8[rs1’ + uimm] = rs2’ uimm ∈ {0,1,2,3}

Fields

§rs1: Reg
§rs2: Reg
§uimm: u8
§

CSh

C.SH mem16[rs1’ + uimm] = rs2’ uimm ∈ {0,2}

Fields

§rs1: Reg
§rs2: Reg
§uimm: u8
§

CZextB

C.ZEXT.B rd’ = rd’ & 0xff

Fields

§rd: Reg
§

CSextB

C.SEXT.B rd’ = sext(rd’[7:0]) (requires Zbb)

Fields

§rd: Reg
§

CZextH

C.ZEXT.H rd’ = rd’ & 0xffff (requires Zbb)

Fields

§rd: Reg
§

CSextH

C.SEXT.H rd’ = sext(rd’[15:0]) (requires Zbb)

Fields

§rd: Reg
§

CZextW

C.ZEXT.W rd’ = rd’ & 0xffff_ffff (requires Zba)

Fields

§rd: Reg
§

CNot

C.NOT rd’ = ~rd’

Fields

§rd: Reg
§

CMul

C.MUL rd’ = (rd’ * rs2’)[XLEN-1:0] (requires M or Zmmul)

Fields

§rd: Reg
§rs2: Reg
§

CmPush

CM.PUSH - push reg_list, decrement sp by stack_adj

stack_adj = urlist.stack_adj_base() + spimm * 16 from the encoding.

Fields

§urlist: ZcmpUrlist<Reg>
§stack_adj: u32
§

CmPop

CM.POP - pop reg_list, increment sp by stack_adj (no return)

Fields

§urlist: ZcmpUrlist<Reg>
§stack_adj: u32
§

CmPopretz

CM.POPRETZ - pop reg_list, set a0=0, increment sp, return

Fields

§urlist: ZcmpUrlist<Reg>
§stack_adj: u32
§

CmPopret

CM.POPRET - pop reg_list, increment sp, return

Fields

§urlist: ZcmpUrlist<Reg>
§stack_adj: u32
§

CmMva01s

CM.MVA01S - a0 = r1s’, a1 = r2s’

Fields

§r1s: Reg
§r2s: Reg
§

CmMvsa01

CM.MVSA01 - r1s’ = a0, r2s’ = a1 (r1s’ != r2s’)

Fields

§r1s: Reg
§r2s: Reg
§

Sll

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Slt

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Srl

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Sra

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Addw

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Subw

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Sllw

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Srlw

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Sraw

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Slti

Fields

§rd: Reg
§rs1: Reg
§imm: i16
§

Sltiu

Fields

§rd: Reg
§rs1: Reg
§imm: i16
§

Xori

Fields

§rd: Reg
§rs1: Reg
§imm: i16
§

Ori

Fields

§rd: Reg
§rs1: Reg
§imm: i16
§

Andi

Fields

§rd: Reg
§rs1: Reg
§imm: i16
§

Srai

Fields

§rd: Reg
§rs1: Reg
§shamt: u8
§

Addiw

Fields

§rd: Reg
§rs1: Reg
§imm: i16
§

Slliw

Fields

§rd: Reg
§rs1: Reg
§shamt: u8
§

Srliw

Fields

§rd: Reg
§rs1: Reg
§shamt: u8
§

Sraiw

Fields

§rd: Reg
§rs1: Reg
§shamt: u8
§

Lb

Fields

§rd: Reg
§rs1: Reg
§imm: i16
§

Lh

Fields

§rd: Reg
§rs1: Reg
§imm: i16
§

Lw

Fields

§rd: Reg
§rs1: Reg
§imm: i16
§

Lhu

Fields

§rd: Reg
§rs1: Reg
§imm: i16
§

Lwu

Fields

§rd: Reg
§rs1: Reg
§imm: i16
§

Sh

Fields

§rs2: Reg
§rs1: Reg
§imm: i16
§

Sw

Fields

§rs2: Reg
§rs1: Reg
§imm: i16
§

Beq

Fields

§rs1: Reg
§rs2: Reg
§imm: i32
§

Bne

Fields

§rs1: Reg
§rs2: Reg
§imm: i32
§

Blt

Fields

§rs1: Reg
§rs2: Reg
§imm: i32
§

Bge

Fields

§rs1: Reg
§rs2: Reg
§imm: i32
§

Bltu

Fields

§rs1: Reg
§rs2: Reg
§imm: i32
§

Bgeu

Fields

§rs1: Reg
§rs2: Reg
§imm: i32
§

Lui

Fields

§rd: Reg
§imm: i32
§

Jal

Fields

§rd: Reg
§imm: i32
§

FenceTso

§

Ebreak

§

Unimp

§

Mulh

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Mulhsu

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Div

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Divu

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Rem

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Remu

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Mulw

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Divw

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Divuw

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Remw

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Remuw

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

AddUw

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Sh1addUw

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Sh2add

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Sh2addUw

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Sh3add

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Sh3addUw

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

SlliUw

Fields

§rd: Reg
§rs1: Reg
§shamt: u8
§

Andn

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Orn

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Xnor

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Clz

Fields

§rd: Reg
§rs1: Reg
§

Clzw

Fields

§rd: Reg
§rs1: Reg
§

Ctz

Fields

§rd: Reg
§rs1: Reg
§

Ctzw

Fields

§rd: Reg
§rs1: Reg
§

Cpop

Fields

§rd: Reg
§rs1: Reg
§

Cpopw

Fields

§rd: Reg
§rs1: Reg
§

Max

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Maxu

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Min

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Minu

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Sextb

Fields

§rd: Reg
§rs1: Reg
§

Sexth

Fields

§rd: Reg
§rs1: Reg
§

Zexth

Fields

§rd: Reg
§rs1: Reg
§

Rol

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Rolw

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Ror

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Rorw

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Orcb

Fields

§rd: Reg
§rs1: Reg
§

Rev8

Fields

§rd: Reg
§rs1: Reg
§

Bset

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Bseti

Fields

§rd: Reg
§rs1: Reg
§shamt: u8
§

Bclr

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Bclri

Fields

§rd: Reg
§rs1: Reg
§shamt: u8
§

Binv

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Binvi

Fields

§rd: Reg
§rs1: Reg
§shamt: u8
§

Bext

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Bexti

Fields

§rd: Reg
§rs1: Reg
§shamt: u8
§

Clmul

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Clmulh

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Clmulr

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Pack

Pack low 32 bits of rs1 and rs2 into rd

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Packh

Pack low 8 bits of rs1 and rs2 into rd bytes 0 and 1

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Packw

Pack low 16 bits of rs1 and rs2 into lower 32 bits of rd, sign-extend

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Brev8

Reverse bits in each byte of rs1

Fields

§rd: Reg
§rs1: Reg
§

Xperm4

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Xperm8

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Aes64Ds

AES final round decryption: InvShiftRows + InvSubBytes, no MixColumns

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Aes64Dsm

AES middle round decryption: InvShiftRows + InvSubBytes + InvMixColumns

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Aes64Im

AES inverse MixColumns on each 32-bit word of rs1

Fields

§rd: Reg
§rs1: Reg
§

Aes64Ks1i

AES key schedule step 1 (rnum in 0..=10)

Fields

§rd: Reg
§rs1: Reg
§rnum: Rv64ZkndKsRnum
§

Aes64Ks2

AES key schedule step 2

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Aes64Es

AES final round encryption: ShiftRows + SubBytes, no MixColumns

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Aes64Esm

AES middle round encryption: ShiftRows + SubBytes + MixColumns

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

Sha256Sig0

Fields

§rd: Reg
§rs1: Reg
§

Sha256Sig1

Fields

§rd: Reg
§rs1: Reg
§

Sha256Sum0

Fields

§rd: Reg
§rs1: Reg
§

Sha256Sum1

Fields

§rd: Reg
§rs1: Reg
§

Sha512Sig0

Fields

§rd: Reg
§rs1: Reg
§

Sha512Sig1

Fields

§rd: Reg
§rs1: Reg
§

Sha512Sum0

Fields

§rd: Reg
§rs1: Reg
§

Sha512Sum1

Fields

§rd: Reg
§rs1: Reg
§

CzeroEqz

czero.eqz rd, rs1, rs2 - move zero to rd if rs2 == 0, else move rs1

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg
§

CzeroNez

czero.nez rd, rs1, rs2 - move zero to rd if rs2 != 0, else move rs1

Fields

§rd: Reg
§rs1: Reg
§rs2: Reg

Implementations§

Source§

impl<Reg> ContractInstructionPrototype<Reg>

Source

pub fn is_jump(&self) -> bool

Check if the instruction is a jump instruction of any kind (affects program counter)

Trait Implementations§

Source§

impl<Reg: Clone> Clone for ContractInstructionPrototype<Reg>

Source§

fn clone(&self) -> ContractInstructionPrototype<Reg>

Returns a duplicate of the value. Read more
1.0.0 · Source§

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more
Source§

impl<Reg: Debug> Debug for ContractInstructionPrototype<Reg>

Source§

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more
§

impl<Reg> Display for ContractInstructionPrototype<Reg>
where Reg: Register,

§

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more
§

impl<Reg, Regs, ExtState, Memory, PC, InstructionHandler, CustomError> ExecutableInstruction<Regs, ExtState, Memory, PC, InstructionHandler, CustomError> for ContractInstructionPrototype<Reg>
where Reg: Register<Type = u64> + ZcmpRegister<Type = u64> + Register, Regs: RegisterFile<Reg>, Memory: VirtualMemory, PC: ProgramCounter<Reg::Type, Memory, CustomError>, InstructionHandler: SystemInstructionHandler<Reg, Regs, Memory, PC, CustomError>,

§

fn execute( self, regs: &mut Regs, _ext_state: &mut ExtState, memory: &mut Memory, program_counter: &mut PC, system_instruction_handler: &mut InstructionHandler, ) -> Result<ControlFlow<()>, ExecutionError<Reg::Type, CustomError>>

Execute instruction. Read more
§

fn prepare_csr_read<C>( csrs: &C, csr_index: u16, raw_value: <Self::Reg as Register>::Type, output_value: &mut <Self::Reg as Register>::Type, ) -> Result<bool, CsrError<CustomError>>
where C: Csrs<Self::Reg, CustomError>,

Prepare CSR read. Read more
§

fn prepare_csr_write<C>( csrs: &mut C, csr_index: u16, write_value: <Self::Reg as Register>::Type, output_value: &mut <Self::Reg as Register>::Type, ) -> Result<bool, CsrError<CustomError>>
where C: Csrs<Self::Reg, CustomError>,

Prepare CSR write. Read more
§

impl<Reg> Instruction for ContractInstructionPrototype<Reg>
where Reg: Register<Type = u64> + ZcmpRegister<Type = u64> + Register,

§

type Reg = Reg

A register type used by the instruction
§

fn try_decode(instruction: u32) -> Option<Self>

Try to decode a single valid instruction
§

fn alignment() -> u8

Instruction alignment in bytes
§

fn size(&self) -> u8

Instruction size in bytes
Source§

impl<Reg: PartialEq> PartialEq for ContractInstructionPrototype<Reg>

Source§

fn eq(&self, other: &ContractInstructionPrototype<Reg>) -> bool

Tests for self and other values to be equal, and is used by ==.
1.0.0 · Source§

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.
Source§

impl<Reg: Copy> Copy for ContractInstructionPrototype<Reg>

Source§

impl<Reg: Eq> Eq for ContractInstructionPrototype<Reg>

Source§

impl<Reg> StructuralPartialEq for ContractInstructionPrototype<Reg>

Auto Trait Implementations§

§

impl<Reg> Freeze for ContractInstructionPrototype<Reg>
where Reg: Freeze,

§

impl<Reg> RefUnwindSafe for ContractInstructionPrototype<Reg>
where Reg: RefUnwindSafe,

§

impl<Reg> Send for ContractInstructionPrototype<Reg>
where Reg: Send,

§

impl<Reg> Sync for ContractInstructionPrototype<Reg>
where Reg: Sync,

§

impl<Reg> Unpin for ContractInstructionPrototype<Reg>
where Reg: Unpin,

§

impl<Reg> UnsafeUnpin for ContractInstructionPrototype<Reg>
where Reg: UnsafeUnpin,

§

impl<Reg> UnwindSafe for ContractInstructionPrototype<Reg>
where Reg: UnwindSafe,

Blanket Implementations§

Source§

impl<T> Any for T
where T: 'static + ?Sized,

Source§

fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
Source§

impl<T> Borrow<T> for T
where T: ?Sized,

Source§

fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
Source§

impl<T> BorrowMut<T> for T
where T: ?Sized,

Source§

fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
Source§

impl<T> CloneToUninit for T
where T: Clone,

Source§

unsafe fn clone_to_uninit(&self, dest: *mut u8)

🔬This is a nightly-only experimental API. (clone_to_uninit)
Performs copy-assignment from self to dest. Read more
Source§

impl<T> From<T> for T

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fn from(t: T) -> T

Returns the argument unchanged.

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impl<T> Instrument for T

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fn instrument(self, span: Span) -> Instrumented<Self>

Instruments this type with the provided [Span], returning an Instrumented wrapper. Read more
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fn in_current_span(self) -> Instrumented<Self>

Instruments this type with the current Span, returning an Instrumented wrapper. Read more
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impl<T, U> Into<U> for T
where U: From<T>,

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fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

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impl<T> IntoEither for T

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fn into_either(self, into_left: bool) -> Either<Self, Self>

Converts self into a Left variant of Either<Self, Self> if into_left is true. Converts self into a Right variant of Either<Self, Self> otherwise. Read more
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fn into_either_with<F>(self, into_left: F) -> Either<Self, Self>
where F: FnOnce(&Self) -> bool,

Converts self into a Left variant of Either<Self, Self> if into_left(&self) returns true. Converts self into a Right variant of Either<Self, Self> otherwise. Read more
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impl<T> Pointable for T

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const ALIGN: usize

The alignment of pointer.
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type Init = T

The type for initializers.
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unsafe fn init(init: <T as Pointable>::Init) -> usize

Initializes a with the given initializer. Read more
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unsafe fn deref<'a>(ptr: usize) -> &'a T

Dereferences the given pointer. Read more
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unsafe fn deref_mut<'a>(ptr: usize) -> &'a mut T

Mutably dereferences the given pointer. Read more
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unsafe fn drop(ptr: usize)

Drops the object pointed to by the given pointer. Read more
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impl<T> Same for T

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type Output = T

Should always be Self
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impl<T> ToOwned for T
where T: Clone,

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type Owned = T

The resulting type after obtaining ownership.
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fn to_owned(&self) -> T

Creates owned data from borrowed data, usually by cloning. Read more
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fn clone_into(&self, target: &mut T)

Uses borrowed data to replace owned data, usually by cloning. Read more
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impl<T> ToString for T
where T: Display + ?Sized,

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fn to_string(&self) -> String

Converts the given value to a String. Read more
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impl<T, U> TryFrom<U> for T
where U: Into<T>,

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type Error = Infallible

The type returned in the event of a conversion error.
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fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.
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impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.
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fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.
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impl<T> WithSubscriber for T

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fn with_subscriber<S>(self, subscriber: S) -> WithDispatch<Self>
where S: Into<Dispatch>,

Attaches the provided Subscriber to this type, returning a [WithDispatch] wrapper. Read more
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fn with_current_subscriber(self) -> WithDispatch<Self>

Attaches the current default Subscriber to this type, returning a [WithDispatch] wrapper. Read more