ab_riscv_primitives/instructions/
zvbc.rs

1//! Zvbc extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::instructions::v::Eew;
8use crate::instructions::v::zvexx::arith::ZveXxArithInstruction;
9use crate::instructions::v::zvexx::carry::ZveXxCarryInstruction;
10use crate::instructions::v::zvexx::config::ZveXxConfigInstruction;
11use crate::instructions::v::zvexx::fixed_point::ZveXxFixedPointInstruction;
12use crate::instructions::v::zvexx::load::{LoadStoreNreg, Nf, SegVmNf, ZveXxLoadInstruction};
13use crate::instructions::v::zvexx::mask::ZveXxMaskInstruction;
14use crate::instructions::v::zvexx::muldiv::ZveXxMulDivInstruction;
15use crate::instructions::v::zvexx::perm::ZveXxPermInstruction;
16use crate::instructions::v::zvexx::reduction::ZveXxReductionInstruction;
17use crate::instructions::v::zvexx::store::ZveXxStoreInstruction;
18use crate::instructions::v::zvexx::widen_narrow::ZveXxWidenNarrowInstruction;
19use crate::instructions::zicsr::ZicsrInstruction;
20use crate::registers::general_purpose::Register;
21use crate::registers::vector::VReg;
22use ab_riscv_macros::instruction;
23use core::fmt;
24
25/// RISC-V Zvbc vector carryless multiplication instruction.
26///
27/// All use the OP-V major opcode (0b101_0111). Encoding spaces:
28///
29/// - `vclmul.[vv,vx]`:  funct6=0b001100, OPMVV/OPMVX; `vm` controls masking (0=masked, 1=unmasked)
30/// - `vclmulh.[vv,vx]`: funct6=0b001101, OPMVV/OPMVX; `vm` controls masking
31///
32/// Both instructions compute a carryless (GF(2)) polynomial product of two SEW-wide elements.
33/// `vclmul` produces the lower SEW bits of the 2*SEW-bit result; `vclmulh` produces the upper
34/// SEW bits. Together they implement full-width carry-less multiplication, as required for
35/// GCM/GHASH (`vclmulh` gives the reduction term) and for CRC computation.
36///
37/// For the `vm` field: `vm=true` means unmasked (process all body elements);
38/// `vm=false` means masked by v0 (skip elements where v0\[i]=0, leaving them undisturbed).
39#[instruction(
40    inherit = [ZveXxInstruction],
41)]
42#[derive(Debug, Clone, Copy, PartialEq, Eq)]
43#[rustfmt::skip]
44pub enum ZvbcInstruction<Reg> {
45    // vclmul: lower SEW bits of the carry-less 2*SEW product
46    /// `vclmul.vv vd, vs2, vs1, vm`
47    VclmulVv  { vd: VReg, vs2: VReg, vs1: VReg, vm: bool },
48    /// `vclmul.vx vd, vs2, rs1, vm`
49    VclmulVx  { vd: VReg, vs2: VReg, rs1: Reg, vm: bool },
50    // vclmulh: upper SEW bits of the carry-less 2*SEW product
51    /// `vclmulh.vv vd, vs2, vs1, vm`
52    VclmulhVv { vd: VReg, vs2: VReg, vs1: VReg, vm: bool },
53    /// `vclmulh.vx vd, vs2, rs1, vm`
54    VclmulhVx { vd: VReg, vs2: VReg, rs1: Reg, vm: bool },
55}
56
57#[instruction]
58impl<Reg> const Instruction for ZvbcInstruction<Reg>
59where
60    Reg: [const] Register,
61{
62    type Reg = Reg;
63
64    #[inline(always)]
65    fn try_decode(instruction: u32) -> Option<Self> {
66        let opcode = (instruction & 0b111_1111) as u8;
67        if opcode != 0b101_0111 {
68            None?;
69        }
70        let vd_bits = ((instruction >> 7) & 0x1f) as u8;
71        let funct3 = ((instruction >> 12) & 0b111) as u8;
72        let vs1_bits = ((instruction >> 15) & 0x1f) as u8;
73        let vs2_bits = ((instruction >> 20) & 0x1f) as u8;
74        // vm=1 means unmasked, vm=0 means masked by v0
75        let vm = ((instruction >> 25) & 1) as u8 == 1;
76        let funct6 = ((instruction >> 26) & 0b11_1111) as u8;
77        let vd = VReg::from_bits(vd_bits)?;
78        let vs2 = VReg::from_bits(vs2_bits)?;
79        match funct3 {
80            // OPMVV: vclmul.vv, vclmulh.vv
81            0b010 => {
82                let vs1 = VReg::from_bits(vs1_bits)?;
83                match funct6 {
84                    0b00_1100 => Some(Self::VclmulVv { vd, vs2, vs1, vm }),
85                    0b00_1101 => Some(Self::VclmulhVv { vd, vs2, vs1, vm }),
86                    _ => None,
87                }
88            }
89            // OPMVX: vclmul.vx, vclmulh.vx
90            0b110 => {
91                let rs1 = Reg::from_bits(vs1_bits)?;
92                match funct6 {
93                    0b00_1100 => Some(Self::VclmulVx { vd, vs2, rs1, vm }),
94                    0b00_1101 => Some(Self::VclmulhVx { vd, vs2, rs1, vm }),
95                    _ => None,
96                }
97            }
98            _ => None,
99        }
100    }
101
102    #[inline(always)]
103    fn alignment() -> u8 {
104        align_of::<u32>() as u8
105    }
106
107    #[inline(always)]
108    fn size(&self) -> u8 {
109        size_of::<u32>() as u8
110    }
111}
112
113#[instruction]
114impl<Reg> fmt::Display for ZvbcInstruction<Reg>
115where
116    Reg: fmt::Display + Copy,
117{
118    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
119        #[rustfmt::skip]
120        match self {
121            Self::VclmulVv  { vd, vs2, vs1, vm } => write!(f, "vclmul.vv {vd}, {vs2}, {vs1}{}", mask_suffix(vm)),
122            Self::VclmulVx  { vd, vs2, rs1, vm } => write!(f, "vclmul.vx {vd}, {vs2}, {rs1}{}", mask_suffix(vm)),
123            Self::VclmulhVv { vd, vs2, vs1, vm } => write!(f, "vclmulh.vv {vd}, {vs2}, {vs1}{}", mask_suffix(vm)),
124            Self::VclmulhVx { vd, vs2, rs1, vm } => write!(f, "vclmulh.vx {vd}, {vs2}, {rs1}{}", mask_suffix(vm)),
125        }
126    }
127}
128
129/// Format mask suffix for display
130#[inline(always)]
131fn mask_suffix(vm: &bool) -> &'static str {
132    if *vm { "" } else { ", v0.t" }
133}
ab_riscv_primitives/instructions/zvbc.rs

ab_riscv_primitives/instructions/
zvbc.rs
