ab_riscv_primitives/instructions/zvbb/
zvkb.rs

1//! Zvkb extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::instructions::v::Eew;
8use crate::instructions::v::zvexx::arith::ZveXxArithInstruction;
9use crate::instructions::v::zvexx::carry::ZveXxCarryInstruction;
10use crate::instructions::v::zvexx::config::ZveXxConfigInstruction;
11use crate::instructions::v::zvexx::fixed_point::ZveXxFixedPointInstruction;
12use crate::instructions::v::zvexx::load::{LoadStoreNreg, Nf, SegVmNf, ZveXxLoadInstruction};
13use crate::instructions::v::zvexx::mask::ZveXxMaskInstruction;
14use crate::instructions::v::zvexx::muldiv::ZveXxMulDivInstruction;
15use crate::instructions::v::zvexx::perm::ZveXxPermInstruction;
16use crate::instructions::v::zvexx::reduction::ZveXxReductionInstruction;
17use crate::instructions::v::zvexx::store::ZveXxStoreInstruction;
18use crate::instructions::v::zvexx::widen_narrow::ZveXxWidenNarrowInstruction;
19use crate::instructions::zicsr::ZicsrInstruction;
20use crate::registers::general_purpose::Register;
21use crate::registers::vector::VReg;
22use ab_riscv_macros::instruction;
23use core::fmt;
24
25/// RISC-V Zvkb vector cryptography bit-manipulation instruction.
26///
27/// All use the OP-V major opcode (0b101_0111). Encoding spaces:
28///
29/// - `vandn.[vv,vx]`: funct6=0b000001, OPIVV/OPIVX; `vm` controls masking (0=masked, 1=unmasked)
30/// - `vbrev8.v`:      funct6=0b010010, OPMVV, vs1=0b01000; `vm` controls masking
31/// - `vrev8.v`:       funct6=0b010010, OPMVV, vs1=0b01001; `vm` controls masking
32/// - `vrol.[vv,vx]`:  funct6=0b010101, OPIVV/OPIVX; `vm` controls masking
33/// - `vror.[vv,vx]`:  funct6=0b010100, OPIVV/OPIVX; `vm` controls masking
34/// - `vror.vi`:       funct6=0b010100, OPIVI; 5-bit unsigned immediate in bits\[19:15] (0-31);
35///   bit\[25] is the standard `vm` field, independent of the immediate
36///
37/// For instructions with a `vm` field: `vm=true` means unmasked (process all body elements);
38/// `vm=false` means masked by v0 (skip elements where v0\[i]=0, leaving them undisturbed).
39#[instruction(
40    inherit = [ZveXxInstruction],
41)]
42#[derive(Debug, Clone, Copy, PartialEq, Eq)]
43#[rustfmt::skip]
44pub enum ZvkbInstruction<Reg> {
45    // vandn: vd[i] = ~vs1[i] & vs2[i]  (or ~rs1 & vs2[i])
46    // Essential for the Chi step of the Keccak permutation (SHA-3).
47
48    /// `vandn.vv vd, vs2, vs1, vm`
49    VandnVv { vd: VReg, vs2: VReg, vs1: VReg, vm: bool },
50    /// `vandn.vx vd, vs2, rs1, vm`
51    VandnVx { vd: VReg, vs2: VReg, rs1: Reg, vm: bool },
52
53    // vbrev8: reverse bits within each byte of each SEW-wide element
54
55    /// `vbrev8.v vd, vs2, vm`
56    Vbrev8V { vd: VReg, vs2: VReg, vm: bool },
57
58    // vrev8: reverse bytes within each SEW-wide element
59
60    /// `vrev8.v vd, vs2, vm`
61    Vrev8V  { vd: VReg, vs2: VReg, vm: bool },
62
63    // vrol: rotate left; no immediate form (use vror.vi with negated immediate instead)
64
65    /// `vrol.vv vd, vs2, vs1, vm`
66    VrolVv  { vd: VReg, vs2: VReg, vs1: VReg, vm: bool },
67    /// `vrol.vx vd, vs2, rs1, vm`
68    VrolVx  { vd: VReg, vs2: VReg, rs1: Reg, vm: bool },
69
70    // vror: rotate right
71    // vror.vi has a 5-bit unsigned immediate in vs1[19:15]; bit[25] is the standard `vm`
72    // mask-control bit
73
74    /// `vror.vv vd, vs2, vs1, vm`
75    VrorVv  { vd: VReg, vs2: VReg, vs1: VReg, vm: bool },
76    /// `vror.vx vd, vs2, rs1, vm`
77    VrorVx  { vd: VReg, vs2: VReg, rs1: Reg, vm: bool },
78    /// `vror.vi vd, vs2, uimm, vm` - `uimm` is 5-bit unsigned (0..=31); `vm` is the
79    /// standard mask-control bit at bit\[25], orthogonal to the immediate.
80    VrorVi  { vd: VReg, vs2: VReg, uimm: u8, vm: bool },
81}
82
83#[instruction]
84impl<Reg> const Instruction for ZvkbInstruction<Reg>
85where
86    Reg: [const] Register,
87{
88    type Reg = Reg;
89
90    #[inline(always)]
91    fn try_decode(instruction: u32) -> Option<Self> {
92        let opcode = (instruction & 0b111_1111) as u8;
93
94        if opcode != 0b101_0111 {
95            None?;
96        }
97
98        let vd_bits = ((instruction >> 7) & 0x1f) as u8;
99        let funct3 = ((instruction >> 12) & 0b111) as u8;
100        let vs1_bits = ((instruction >> 15) & 0x1f) as u8;
101        let vs2_bits = ((instruction >> 20) & 0x1f) as u8;
102        // vm=1 means unmasked, vm=0 means masked by v0
103        let vm = ((instruction >> 25) & 1) as u8 == 1;
104        let funct6 = ((instruction >> 26) & 0b11_1111) as u8;
105
106        let vd = VReg::from_bits(vd_bits)?;
107        let vs2 = VReg::from_bits(vs2_bits)?;
108
109        match funct3 {
110            // OPIVV: vandn.vv, vrol.vv, vror.vv
111            0b000 => {
112                let vs1 = VReg::from_bits(vs1_bits)?;
113                match funct6 {
114                    0b00_0001 => Some(Self::VandnVv { vd, vs2, vs1, vm }),
115                    0b01_0100 => Some(Self::VrorVv { vd, vs2, vs1, vm }),
116                    0b01_0101 => Some(Self::VrolVv { vd, vs2, vs1, vm }),
117                    _ => None,
118                }
119            }
120            // OPIVX: vandn.vx, vrol.vx, vror.vx
121            0b100 => {
122                let rs1 = Reg::from_bits(vs1_bits)?;
123                match funct6 {
124                    0b00_0001 => Some(Self::VandnVx { vd, vs2, rs1, vm }),
125                    0b01_0100 => Some(Self::VrorVx { vd, vs2, rs1, vm }),
126                    0b01_0101 => Some(Self::VrolVx { vd, vs2, rs1, vm }),
127                    _ => None,
128                }
129            }
130            // OPIVI: vror.vi only - 5-bit unsigned immediate in vs1[19:15]; bit[25] is the standard
131            // vm mask-control bit
132            0b011 => {
133                if funct6 != 0b01_0100 {
134                    None?;
135                }
136                // vm_bit here is imm[5]; reconstruct 6-bit unsigned immediate
137                // uimm is 5-bit (0-31); bit[25] is a standard vm field, not imm[5]
138                let uimm = vs1_bits;
139                Some(Self::VrorVi { vd, vs2, uimm, vm })
140            }
141            // OPMVV: vbrev8.v and vrev8.v - unary, vs1 encodes the sub-operation
142            // funct6=0b010010 (VXUNARY0 sub-space); sub-opcodes 0b01000/0b01001 belong
143            // to Zvkb; other sub-opcodes in this space (vzext, vsext) are not claimed here
144            0b010 => {
145                if funct6 != 0b01_0010 {
146                    None?;
147                }
148                match vs1_bits {
149                    0b01000 => Some(Self::Vbrev8V { vd, vs2, vm }),
150                    0b01001 => Some(Self::Vrev8V { vd, vs2, vm }),
151                    _ => None,
152                }
153            }
154            _ => None,
155        }
156    }
157
158    #[inline(always)]
159    fn alignment() -> u8 {
160        align_of::<u32>() as u8
161    }
162
163    #[inline(always)]
164    fn size(&self) -> u8 {
165        size_of::<u32>() as u8
166    }
167}
168
169#[instruction]
170impl<Reg> fmt::Display for ZvkbInstruction<Reg>
171where
172    Reg: fmt::Display + Copy,
173{
174    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
175        #[rustfmt::skip]
176        match self {
177            Self::VandnVv { vd, vs2, vs1, vm }  => write!(f, "vandn.vv {vd}, {vs2}, {vs1}{}", mask_suffix(vm)),
178            Self::VandnVx { vd, vs2, rs1, vm }  => write!(f, "vandn.vx {vd}, {vs2}, {rs1}{}", mask_suffix(vm)),
179            Self::Vbrev8V { vd, vs2, vm }       => write!(f, "vbrev8.v {vd}, {vs2}{}", mask_suffix(vm)),
180            Self::Vrev8V  { vd, vs2, vm }       => write!(f, "vrev8.v {vd}, {vs2}{}", mask_suffix(vm)),
181            Self::VrolVv  { vd, vs2, vs1, vm }  => write!(f, "vrol.vv {vd}, {vs2}, {vs1}{}", mask_suffix(vm)),
182            Self::VrolVx  { vd, vs2, rs1, vm }  => write!(f, "vrol.vx {vd}, {vs2}, {rs1}{}", mask_suffix(vm)),
183            Self::VrorVv  { vd, vs2, vs1, vm }  => write!(f, "vror.vv {vd}, {vs2}, {vs1}{}", mask_suffix(vm)),
184            Self::VrorVx  { vd, vs2, rs1, vm }  => write!(f, "vror.vx {vd}, {vs2}, {rs1}{}", mask_suffix(vm)),
185            Self::VrorVi  { vd, vs2, uimm, vm } => write!(f, "vror.vi {vd}, {vs2}, {uimm}{}", mask_suffix(vm)),
186        }
187    }
188}
189
190/// Format mask suffix for display
191#[inline(always)]
192fn mask_suffix(vm: &bool) -> &'static str {
193    if *vm { "" } else { ", v0.t" }
194}
ab_riscv_primitives/instructions/zvbb/zvkb.rs

ab_riscv_primitives/instructions/zvbb/
zvkb.rs
