ab_riscv_primitives/instructions/
zicond.rs

1//! Zicond extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11/// RISC-V Zicond instruction (Integer Conditional Operations)
12#[instruction]
13#[derive(Debug, Clone, Copy, PartialEq, Eq)]
14pub enum ZicondInstruction<Reg> {
15    /// `czero.eqz rd, rs1, rs2` - move zero to `rd` if `rs2 == 0`, else move `rs1`
16    CzeroEqz { rd: Reg, rs1: Reg, rs2: Reg },
17    /// `czero.nez rd, rs1, rs2` - move zero to `rd` if `rs2 != 0`, else move `rs1`
18    CzeroNez { rd: Reg, rs1: Reg, rs2: Reg },
19}
20
21#[instruction]
22const impl<Reg> Instruction for ZicondInstruction<Reg>
23where
24    Reg: [const] Register,
25{
26    type Reg = Reg;
27
28    #[inline(always)]
29    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
30    fn try_decode(instruction: u32) -> Option<Self> {
31        let opcode = (instruction & 0b111_1111) as u8;
32        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
33        let funct3 = ((instruction >> 12) & 0b111) as u8;
34        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
35        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
36        let funct7 = ((instruction >> 25) & 0x7f) as u8;
37
38        // Both Zicond instructions share opcode=0x33 (OP) and funct7=0x07
39        match (opcode, funct7) {
40            (0b011_0011, 0b000_0111) => {
41                let rd = Reg::from_bits(rd_bits)?;
42                let rs1 = Reg::from_bits(rs1_bits)?;
43                let rs2 = Reg::from_bits(rs2_bits)?;
44                match funct3 {
45                    0b101 => Some(Self::CzeroEqz { rd, rs1, rs2 }),
46                    0b111 => Some(Self::CzeroNez { rd, rs1, rs2 }),
47                    _ => None,
48                }
49            }
50            _ => None,
51        }
52    }
53
54    #[inline(always)]
55    fn alignment() -> u8 {
56        align_of::<u32>() as u8
57    }
58
59    #[inline(always)]
60    fn size(&self) -> u8 {
61        size_of::<u32>() as u8
62    }
63}
64
65impl<Reg> fmt::Display for ZicondInstruction<Reg>
66where
67    Reg: fmt::Display,
68{
69    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
70        match self {
71            Self::CzeroEqz { rd, rs1, rs2 } => write!(f, "czero.eqz {rd}, {rs1}, {rs2}"),
72            Self::CzeroNez { rd, rs1, rs2 } => write!(f, "czero.nez {rd}, {rs1}, {rs2}"),
73        }
74    }
75}
ab_riscv_primitives/instructions/zicond.rs

ab_riscv_primitives/instructions/
zicond.rs
