ab_riscv_primitives/instructions/
zawrs.rs1#[cfg(test)]
4mod tests;
5
6use crate::hart::HartConfig;
7use crate::instructions::{ImplementedExtension, Instruction, IsaExtension};
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12#[instruction]
14#[derive(Debug, Clone, Copy)]
15#[derive_const(PartialEq, Eq)]
16pub enum ZawrsInstruction<Hart>
17where
18 Hart: HartConfig,
19{
20 WrsNto,
22 WrsSto,
24}
25
26#[instruction]
27const impl<Reg, Hart> Instruction for ZawrsInstruction<Hart>
28where
29 Reg: [const] Register,
30 Hart: [const] HartConfig<Reg = Reg>,
31{
32 const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = &[IsaExtension::new("zawrs", 1, 0)];
33
34 const ALIGNMENT: u8 = align_of::<u32>() as u8;
35
36 type Hart = Hart;
37
38 #[inline(always)]
39 #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
40 fn try_decode(instruction: u32) -> Option<Self> {
41 let opcode = (instruction & 0b111_1111) as u8;
42 let rd_bits = ((instruction >> 7) & 0x1f) as u8;
43 let funct3 = ((instruction >> 12) & 0b111) as u8;
44 let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
45 let imm = (instruction >> 20) & 0xfff;
46
47 match (opcode, funct3, rd_bits, rs1_bits, imm) {
48 (0b111_0011, 0b000, 0, 0, 0x00d) => Some(Self::WrsNto),
49 (0b111_0011, 0b000, 0, 0, 0x01d) => Some(Self::WrsSto),
50 _ => None,
51 }
52 }
53
54 #[inline(always)]
55 fn size(&self) -> u8 {
56 size_of::<u32>() as u8
57 }
58}
59
60#[instruction]
61impl<Reg, Hart> fmt::Display for ZawrsInstruction<Hart>
62where
63 Reg: fmt::Display,
64 Hart: HartConfig<Reg = Reg>,
65{
66 fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
67 match self {
68 Self::WrsNto => write!(f, "wrs.nto"),
69 Self::WrsSto => write!(f, "wrs.sto"),
70 }
71 }
72}