ab_riscv_primitives/instructions/
zawrs.rs

1//! Zawrs extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11/// RISC-V Zawrs instruction (Wait-on-Reservation-Set)
12#[instruction]
13#[derive(Debug, Clone, Copy)]
14#[derive_const(PartialEq, Eq)]
15pub enum ZawrsInstruction<Reg> {
16    /// Wait-on-Reservation-Set, no timeout
17    WrsNto,
18    /// Wait-on-Reservation-Set, short timeout
19    WrsSto,
20}
21
22#[instruction]
23const impl<Reg> Instruction for ZawrsInstruction<Reg>
24where
25    Reg: [const] Register,
26{
27    const ALIGNMENT: u8 = align_of::<u32>() as u8;
28
29    type Reg = Reg;
30
31    #[inline(always)]
32    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
33    fn try_decode(instruction: u32) -> Option<Self> {
34        let opcode = (instruction & 0b111_1111) as u8;
35        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
36        let funct3 = ((instruction >> 12) & 0b111) as u8;
37        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
38        let imm = (instruction >> 20) & 0xfff;
39
40        match (opcode, funct3, rd_bits, rs1_bits, imm) {
41            (0b111_0011, 0b000, 0, 0, 0x00d) => Some(Self::WrsNto),
42            (0b111_0011, 0b000, 0, 0, 0x01d) => Some(Self::WrsSto),
43            _ => None,
44        }
45    }
46
47    #[inline(always)]
48    fn size(&self) -> u8 {
49        size_of::<u32>() as u8
50    }
51}
52
53#[instruction]
54impl<Reg> fmt::Display for ZawrsInstruction<Reg>
55where
56    Reg: fmt::Display,
57{
58    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
59        match self {
60            Self::WrsNto => write!(f, "wrs.nto"),
61            Self::WrsSto => write!(f, "wrs.sto"),
62        }
63    }
64}
ab_riscv_primitives/instructions/zawrs.rs

ab_riscv_primitives/instructions/
zawrs.rs
