ab_riscv_primitives/instructions/v/zvexx/
load.rs

1//! ZveXx vector load instructions
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::instructions::v::{Eew, V};
8use crate::registers::general_purpose::Register;
9use crate::registers::vector::VReg;
10use ab_riscv_macros::instruction;
11use core::fmt;
12
13/// Number of fields per segment for load/store instructions
14#[derive(Debug, Clone, Copy)]
15#[derive_const(PartialEq, Eq)]
16#[repr(u8)]
17pub enum Nf {
18    /// 1 field per segment
19    N1 = 1,
20    /// 2 fields per segment
21    N2 = 2,
22    /// 3 fields per segment
23    N3 = 3,
24    /// 4 fields per segment
25    N4 = 4,
26    /// 5 fields per segment
27    N5 = 5,
28    /// 6 fields per segment
29    N6 = 6,
30    /// 7 fields per segment
31    N7 = 7,
32    /// 8 fields per segment
33    N8 = 8,
34}
35
36impl fmt::Display for Nf {
37    #[inline]
38    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
39        fmt::Display::fmt(&self.fields_per_segment(), f)
40    }
41}
42
43impl Nf {
44    /// Maximum allowed value for `Nf`
45    pub const MAX: Self = Nf::N8;
46
47    /// Create a new instance.
48    ///
49    /// `nf` must be in the range `1..=8` or `None` is returned.
50    #[inline(always)]
51    pub const fn new(nf: u8) -> Option<Self> {
52        match nf {
53            1 => Some(Nf::N1),
54            2 => Some(Nf::N2),
55            3 => Some(Nf::N3),
56            4 => Some(Nf::N4),
57            5 => Some(Nf::N5),
58            6 => Some(Nf::N6),
59            7 => Some(Nf::N7),
60            8 => Some(Nf::N8),
61            _ => None,
62        }
63    }
64
65    /// Returns the number of fields per segment for the load/store instruction.
66    ///
67    /// Always in `1..=8` range.
68    #[inline(always)]
69    pub const fn fields_per_segment(&self) -> u8 {
70        *self as u8
71    }
72}
73
74/// `vm` and `nf` fields for segmented load/store instructions.
75///
76/// This is a more compact representation that fits within a single byte rather than two when
77/// storing these separately.
78#[derive(Debug, Clone, Copy)]
79#[derive_const(PartialEq, Eq)]
80pub struct SegVmNf(u8);
81
82impl SegVmNf {
83    /// Create a new instance
84    #[inline(always)]
85    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic)]
86    pub const fn new(vm: bool, nf: Nf) -> Self {
87        Self((nf.fields_per_segment() << 1) | u8::from(vm))
88    }
89
90    /// Extracts the `vm` field from the `SegVmNf` representation
91    #[inline(always)]
92    pub const fn vm(&self) -> bool {
93        self.0 & 1 == 1
94    }
95
96    /// Extracts the `nf` field from the `SegVmNf` representation
97    #[inline(always)]
98    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic)]
99    pub const fn nf(&self) -> Nf {
100        // SAFETY: Protected internal invariant
101        unsafe { Nf::new(self.0 >> 1).unwrap_unchecked() }
102    }
103}
104
105/// `nreg` field for load/store instructions
106#[derive(Debug, Clone, Copy)]
107#[derive_const(PartialEq, Eq)]
108#[repr(u8)]
109pub enum LoadStoreNreg {
110    /// 1 register
111    N1 = 1,
112    /// 2 registers
113    N2 = 2,
114    /// 4 registers
115    N4 = 4,
116    /// 8 registers
117    N8 = 8,
118}
119
120impl fmt::Display for LoadStoreNreg {
121    #[inline]
122    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
123        fmt::Display::fmt(&self.num_registers(), f)
124    }
125}
126
127impl LoadStoreNreg {
128    /// Create a new instance
129    #[inline(always)]
130    pub const fn new(n: u8) -> Option<Self> {
131        match n {
132            1 => Some(Self::N1),
133            2 => Some(Self::N2),
134            4 => Some(Self::N4),
135            8 => Some(Self::N8),
136            _ => None,
137        }
138    }
139
140    /// Get the number of registers
141    #[inline(always)]
142    pub const fn num_registers(&self) -> u8 {
143        *self as u8
144    }
145}
146
147/// RISC-V ZveXx vector load instruction.
148///
149/// Encoded under the LOAD-FP major opcode (0x07). All loads use rs1 (GPR) as a base address and vd
150/// (vector register) as a destination.
151#[instruction]
152#[derive(Debug, Clone, Copy)]
153#[derive_const(PartialEq, Eq)]
154#[rustfmt::skip]
155#[doc(hidden)]
156pub enum ZveXxLoadInstruction<Reg> {
157    /// Unit-stride load: `vle{eew}.v vd, (rs1), vm`
158    ///
159    /// mop=00, lumop=00000, nf=000
160    Vle { vd: VReg, rs1: Reg, vm: bool, eew: Eew },
161    /// Unit-stride fault-only-first load: `vle{eew}ff.v vd, (rs1), vm`
162    ///
163    /// mop=00, lumop=10000, nf=000
164    Vleff { vd: VReg, rs1: Reg, vm: bool, eew: Eew },
165    /// Unit-stride mask load: `vlm.v vd, (rs1)`
166    ///
167    /// mop=00, lumop=01011, nf=000, eew=e8, vm=1
168    Vlm { vd: VReg, rs1: Reg },
169    /// Strided load: `vlse{eew}.v vd, (rs1), rs2, vm`
170    ///
171    /// mop=10, nf=000
172    Vlse { vd: VReg, rs1: Reg, rs2: Reg, vm: bool, eew: Eew },
173    /// Indexed-unordered load: `vluxei{eew}.v vd, (rs1), vs2, vm`
174    ///
175    /// mop=01, nf=000. eew is the index element width.
176    Vluxei { vd: VReg, rs1: Reg, vs2: VReg, vm: bool, eew: Eew },
177    /// Indexed-ordered load: `vloxei{eew}.v vd, (rs1), vs2, vm`
178    ///
179    /// mop=11, nf=000. eew is the index element width.
180    Vloxei { vd: VReg, rs1: Reg, vs2: VReg, vm: bool, eew: Eew },
181    /// Whole-register load: `vl{nreg}re{eew}.v vd, (rs1)`
182    ///
183    /// mop=00, lumop=01000, vm=1. nreg must be 1, 2, 4, or 8.
184    Vlr { vd: VReg, rs1: Reg, nreg: LoadStoreNreg, eew: Eew },
185    /// Unit-stride segment load: `vlseg{nf}e{eew}.v vd, (rs1), vm`
186    ///
187    /// mop=00, lumop=00000, nf>0
188    Vlseg { vd: VReg, rs1: Reg, eew: Eew, vm_nf: SegVmNf },
189    /// Unit-stride fault-only-first segment load: `vlseg{nf}e{eew}ff.v vd, (rs1), vm`
190    ///
191    /// mop=00, lumop=10000, nf>0
192    Vlsegff { vd: VReg, rs1: Reg, eew: Eew, vm_nf: SegVmNf },
193    /// Strided segment load: `vlsseg{nf}e{eew}.v vd, (rs1), rs2, vm`
194    ///
195    /// mop=10, nf>0
196    Vlsseg { vd: VReg, rs1: Reg, rs2: Reg, eew: Eew, vm_nf: SegVmNf },
197    /// Indexed-unordered segment load: `vluxseg{nf}ei{eew}.v vd, (rs1), vs2, vm`
198    ///
199    /// mop=01, nf>0
200    Vluxseg { vd: VReg, rs1: Reg, vs2: VReg, eew: Eew, vm_nf: SegVmNf },
201    /// Indexed-ordered segment load: `vloxseg{nf}ei{eew}.v vd, (rs1), vs2, vm`
202    ///
203    /// mop=11, nf>0
204    Vloxseg { vd: VReg, rs1: Reg, vs2: VReg, eew: Eew, vm_nf: SegVmNf },
205}
206
207#[instruction]
208const impl<Reg> Instruction for ZveXxLoadInstruction<Reg>
209where
210    Reg: [const] Register,
211{
212    type Reg = Reg;
213
214    #[inline(always)]
215    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
216    fn try_decode(instruction: u32) -> Option<Self> {
217        let opcode = (instruction & 0b111_1111) as u8;
218
219        // LOAD-FP major opcode
220        if opcode != 0b000_0111 {
221            None?;
222        }
223
224        let vd_bits = ((instruction >> 7) & 0x1f) as u8;
225        let width = ((instruction >> 12) & 0b111) as u8;
226        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
227        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
228        let vm = ((instruction >> 25) & 1) != 0;
229        let mop = ((instruction >> 26) & 0b11) as u8;
230        let mew = ((instruction >> 28) & 1) as u8;
231        let nf = ((instruction >> 29) & 0b111) as u8;
232
233        // mew must be 0 (reserved for >=128-bit)
234        if mew != 0 {
235            None?;
236        }
237
238        let vd = VReg::from_bits(vd_bits)?;
239        let rs1 = Reg::from_bits(rs1_bits)?;
240
241        // nf encodes number of fields minus 1 (nf=0 means 1 field)
242        let nf_val = nf + 1;
243
244        match mop {
245            // Unit-stride
246            0b00 => {
247                let lumop = rs2_bits;
248                match lumop {
249                    // Regular unit-stride load
250                    0b0_0000 => {
251                        let eew = Eew::from_width(width)?;
252                        if nf == 0 {
253                            Some(Self::Vle { vd, rs1, vm, eew })
254                        } else {
255                            Some(Self::Vlseg {
256                                vd,
257                                rs1,
258                                eew,
259                                vm_nf: SegVmNf::new(vm, Nf::new(nf_val)?),
260                            })
261                        }
262                    }
263                    // Whole-register load
264                    0b0_1000 => {
265                        // vm must be 1 (unmasked)
266                        if !vm {
267                            None?;
268                        }
269                        let eew = Eew::from_width(width)?;
270                        let nreg = LoadStoreNreg::new(nf_val)?;
271                        Some(Self::Vlr { vd, rs1, nreg, eew })
272                    }
273                    // Mask load
274                    0b0_1011 => {
275                        // Must be eew=e8, vm=1, nf=0
276                        if width != 0b000 || !vm || nf != 0 {
277                            None?;
278                        }
279                        Some(Self::Vlm { vd, rs1 })
280                    }
281                    // Fault-only-first
282                    0b1_0000 => {
283                        let eew = Eew::from_width(width)?;
284                        if nf == 0 {
285                            Some(Self::Vleff { vd, rs1, vm, eew })
286                        } else {
287                            Some(Self::Vlsegff {
288                                vd,
289                                rs1,
290                                eew,
291                                vm_nf: SegVmNf::new(vm, Nf::new(nf_val)?),
292                            })
293                        }
294                    }
295                    _ => None,
296                }
297            }
298            // Indexed-unordered
299            0b01 => {
300                let eew = Eew::from_width(width)?;
301                let vs2 = VReg::from_bits(rs2_bits)?;
302
303                if !Self::implements_extension::<V<_>>()
304                    && Reg::XLEN == u32::BITS as u8
305                    && eew == Eew::E64
306                {
307                    None?;
308                }
309
310                if nf == 0 {
311                    Some(Self::Vluxei {
312                        vd,
313                        rs1,
314                        vs2,
315                        vm,
316                        eew,
317                    })
318                } else {
319                    Some(Self::Vluxseg {
320                        vd,
321                        rs1,
322                        vs2,
323                        eew,
324                        vm_nf: SegVmNf::new(vm, Nf::new(nf_val)?),
325                    })
326                }
327            }
328            // Strided
329            0b10 => {
330                let eew = Eew::from_width(width)?;
331                let rs2 = Reg::from_bits(rs2_bits)?;
332                if nf == 0 {
333                    Some(Self::Vlse {
334                        vd,
335                        rs1,
336                        rs2,
337                        vm,
338                        eew,
339                    })
340                } else {
341                    Some(Self::Vlsseg {
342                        vd,
343                        rs1,
344                        rs2,
345                        eew,
346                        vm_nf: SegVmNf::new(vm, Nf::new(nf_val)?),
347                    })
348                }
349            }
350            // Indexed-ordered
351            0b11 => {
352                let eew = Eew::from_width(width)?;
353                let vs2 = VReg::from_bits(rs2_bits)?;
354
355                if !Self::implements_extension::<V<_>>()
356                    && Reg::XLEN == u32::BITS as u8
357                    && eew == Eew::E64
358                {
359                    None?;
360                }
361
362                if nf == 0 {
363                    Some(Self::Vloxei {
364                        vd,
365                        rs1,
366                        vs2,
367                        vm,
368                        eew,
369                    })
370                } else {
371                    Some(Self::Vloxseg {
372                        vd,
373                        rs1,
374                        vs2,
375                        eew,
376                        vm_nf: SegVmNf::new(vm, Nf::new(nf_val)?),
377                    })
378                }
379            }
380            _ => None,
381        }
382    }
383
384    #[inline(always)]
385    fn alignment() -> u8 {
386        align_of::<u32>() as u8
387    }
388
389    #[inline(always)]
390    fn size(&self) -> u8 {
391        size_of::<u32>() as u8
392    }
393}
394
395#[instruction]
396impl<Reg> fmt::Display for ZveXxLoadInstruction<Reg>
397where
398    Reg: fmt::Display,
399{
400    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
401        #[rustfmt::skip]
402        match self {
403            Self::Vle { vd, rs1, vm, eew } => write!(f, "vle{eew}.v {vd}, ({rs1}){}", mask_suffix(vm)),
404            Self::Vleff { vd, rs1, vm, eew } => write!(f, "vle{eew}ff.v {vd}, ({rs1}){}", mask_suffix(vm)),
405            Self::Vlm { vd, rs1 } => write!(f, "vlm.v {vd}, ({rs1})"),
406            Self::Vlse { vd, rs1, rs2, vm, eew } => write!(f, "vlse{eew}.v {vd}, ({rs1}), {rs2}{}", mask_suffix(vm)),
407            Self::Vluxei { vd, rs1, vs2, vm, eew } => write!(f, "vluxei{eew}.v {vd}, ({rs1}), {vs2}{}", mask_suffix(vm)),
408            Self::Vloxei { vd, rs1, vs2, vm, eew } => write!(f, "vloxei{eew}.v {vd}, ({rs1}), {vs2}{}", mask_suffix(vm)),
409            Self::Vlr { vd, rs1, nreg, eew } => write!(f, "vl{nreg}re{eew}.v {vd}, ({rs1})"),
410            Self::Vlseg { vd, rs1, eew, vm_nf } => write!(f, "vlseg{}e{eew}.v {vd}, ({rs1}){}", vm_nf.nf(), mask_suffix(&vm_nf.vm())),
411            Self::Vlsegff { vd, rs1, eew, vm_nf } => write!(f, "vlseg{}e{eew}ff.v {vd}, ({rs1}){}", vm_nf.nf(), mask_suffix(&vm_nf.vm())),
412            Self::Vlsseg { vd, rs1, rs2, eew, vm_nf } => write!(f, "vlsseg{}e{eew}.v {vd}, ({rs1}), {rs2}{}", vm_nf.nf(), mask_suffix(&vm_nf.vm())),
413            Self::Vluxseg { vd, rs1, vs2, eew, vm_nf } => write!(f, "vluxseg{}ei{eew}.v {vd}, ({rs1}), {vs2}{}", vm_nf.nf(), mask_suffix(&vm_nf.vm())),
414            Self::Vloxseg { vd, rs1, vs2, eew, vm_nf } => write!(f, "vloxseg{}ei{eew}.v {vd}, ({rs1}), {vs2}{}", vm_nf.nf(), mask_suffix(&vm_nf.vm())),
415        }
416    }
417}
418
419/// Format mask suffix for display
420#[inline(always)]
421fn mask_suffix(vm: &bool) -> &'static str {
422    if *vm { "" } else { ", v0.t" }
423}
ab_riscv_primitives/instructions/v/zvexx/load.rs

ab_riscv_primitives/instructions/v/zvexx/
load.rs
