ab_riscv_primitives/instructions/v/
zvexx.rs

1//! ZveXx extension (Vector Extension for Embedded Processors, ELEN=64, integer-only)
2
3#[doc(hidden)]
4pub mod arith;
5#[doc(hidden)]
6pub mod carry;
7#[doc(hidden)]
8pub mod config;
9#[doc(hidden)]
10pub mod fixed_point;
11#[doc(hidden)]
12pub mod load;
13#[doc(hidden)]
14pub mod mask;
15#[doc(hidden)]
16pub mod muldiv;
17#[doc(hidden)]
18pub mod perm;
19#[doc(hidden)]
20pub mod reduction;
21#[doc(hidden)]
22pub mod store;
23#[doc(hidden)]
24pub mod widen_narrow;
25
26use crate::instructions::Instruction;
27use crate::instructions::v::zvexx::arith::ZveXxArithInstruction;
28use crate::instructions::v::zvexx::carry::ZveXxCarryInstruction;
29use crate::instructions::v::zvexx::config::ZveXxConfigInstruction;
30use crate::instructions::v::zvexx::fixed_point::ZveXxFixedPointInstruction;
31use crate::instructions::v::zvexx::load::{LoadStoreNreg, Nf, SegVmNf, ZveXxLoadInstruction};
32use crate::instructions::v::zvexx::mask::ZveXxMaskInstruction;
33use crate::instructions::v::zvexx::muldiv::ZveXxMulDivInstruction;
34use crate::instructions::v::zvexx::perm::ZveXxPermInstruction;
35use crate::instructions::v::zvexx::reduction::ZveXxReductionInstruction;
36use crate::instructions::v::zvexx::store::ZveXxStoreInstruction;
37use crate::instructions::v::zvexx::widen_narrow::ZveXxWidenNarrowInstruction;
38use crate::instructions::v::{Eew, V};
39use crate::instructions::zicsr::ZicsrInstruction;
40use crate::registers::general_purpose::Register;
41use crate::registers::vector::VReg;
42use ab_riscv_macros::instruction;
43use core::fmt;
44
45/// RISC-V ZveXx instruction.
46///
47/// `X` is any legal value, according to the RISC-V specification, for example, Zve32x or Zve64x.
48/// The actual `ELEN` and `VLEN` values are configured at the execution side and do not impact
49/// decoded instructions.
50#[instruction(
51    inherit = [
52        ZveXxConfigInstruction,
53        ZveXxLoadInstruction,
54        ZveXxStoreInstruction,
55        ZveXxArithInstruction,
56        ZveXxCarryInstruction,
57        ZveXxMulDivInstruction,
58        ZveXxWidenNarrowInstruction,
59        ZveXxFixedPointInstruction,
60        ZveXxMaskInstruction,
61        ZveXxReductionInstruction,
62        ZveXxPermInstruction,
63        ZicsrInstruction,
64    ],
65)]
66#[derive(Debug, Clone, Copy)]
67#[derive_const(PartialEq, Eq)]
68pub enum ZveXxInstruction<Reg> {}
69
70#[instruction]
71const impl<Reg> Instruction for ZveXxInstruction<Reg>
72where
73    Reg: [const] Register,
74{
75    const ALIGNMENT: u8 = align_of::<u32>() as u8;
76
77    type Reg = Reg;
78
79    #[inline(always)]
80    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
81    fn try_decode(instruction: u32) -> Option<Self> {
82        None
83    }
84
85    #[inline(always)]
86    fn size(&self) -> u8 {
87        size_of::<u32>() as u8
88    }
89}
90
91#[instruction]
92impl<Reg> fmt::Display for ZveXxInstruction<Reg>
93where
94    Reg: fmt::Display + Copy,
95{
96    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
97        match self {}
98    }
99}
ab_riscv_primitives/instructions/v/zvexx.rs

ab_riscv_primitives/instructions/v/
zvexx.rs
