ab_riscv_primitives/instructions/v/
zve64x.rs

1//! Zve64x extension (Vector Extension for Embedded Processors, ELEN=64, integer-only)
2
3#[doc(hidden)]
4pub mod arith;
5#[doc(hidden)]
6pub mod config;
7#[doc(hidden)]
8pub mod fixed_point;
9#[doc(hidden)]
10pub mod load;
11#[doc(hidden)]
12pub mod mask;
13#[doc(hidden)]
14pub mod muldiv;
15#[doc(hidden)]
16pub mod perm;
17#[doc(hidden)]
18pub mod reduction;
19#[doc(hidden)]
20pub mod store;
21#[doc(hidden)]
22pub mod widen_narrow;
23
24use crate::instructions::Instruction;
25use crate::instructions::v::Eew;
26use crate::instructions::v::zve64x::arith::Zve64xArithInstruction;
27use crate::instructions::v::zve64x::config::Zve64xConfigInstruction;
28use crate::instructions::v::zve64x::fixed_point::Zve64xFixedPointInstruction;
29use crate::instructions::v::zve64x::load::Zve64xLoadInstruction;
30use crate::instructions::v::zve64x::mask::Zve64xMaskInstruction;
31use crate::instructions::v::zve64x::muldiv::Zve64xMulDivInstruction;
32use crate::instructions::v::zve64x::perm::Zve64xPermInstruction;
33use crate::instructions::v::zve64x::reduction::Zve64xReductionInstruction;
34use crate::instructions::v::zve64x::store::Zve64xStoreInstruction;
35use crate::instructions::v::zve64x::widen_narrow::Zve64xWidenNarrowInstruction;
36use crate::instructions::zicsr::ZicsrInstruction;
37use crate::registers::general_purpose::Register;
38use crate::registers::vector::VReg;
39use ab_riscv_macros::instruction;
40use core::fmt;
41
42/// RISC-V Zve64x instruction
43#[instruction(
44    inherit = [
45        Zve64xConfigInstruction,
46        Zve64xLoadInstruction,
47        Zve64xStoreInstruction,
48        Zve64xArithInstruction,
49        Zve64xMulDivInstruction,
50        Zve64xWidenNarrowInstruction,
51        Zve64xFixedPointInstruction,
52        Zve64xMaskInstruction,
53        Zve64xReductionInstruction,
54        Zve64xPermInstruction,
55        ZicsrInstruction,
56    ],
57)]
58#[derive(Debug, Clone, Copy, PartialEq, Eq)]
59pub enum Zve64xInstruction<Reg> {}
60
61#[instruction]
62impl<Reg> const Instruction for Zve64xInstruction<Reg>
63where
64    Reg: [const] Register,
65{
66    type Reg = Reg;
67
68    #[inline(always)]
69    fn try_decode(instruction: u32) -> Option<Self> {
70        None
71    }
72
73    #[inline(always)]
74    fn alignment() -> u8 {
75        align_of::<u32>() as u8
76    }
77
78    #[inline(always)]
79    fn size(&self) -> u8 {
80        size_of::<u32>() as u8
81    }
82}
83
84#[instruction]
85impl<Reg> fmt::Display for Zve64xInstruction<Reg>
86where
87    Reg: fmt::Display + Copy,
88{
89    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
90        match self {}
91    }
92}
ab_riscv_primitives/instructions/v/zve64x.rs

ab_riscv_primitives/instructions/v/
zve64x.rs
