ab_riscv_primitives/instructions/rv64/zk/zkn/
zknh.rs

1//! RV64 Zknh extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::hart::HartConfig;
7use crate::instructions::{ImplementedExtension, Instruction, IsaExtension};
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12/// RISC-V RV64 Zknh instruction (SHA-256 and SHA-512 sigma functions)
13#[instruction]
14#[derive(Debug, Clone, Copy)]
15#[derive_const(PartialEq, Eq)]
16pub enum Rv64ZknhInstruction<Hart>
17where
18    Hart: HartConfig,
19{
20    Sha256Sig0 { rd: Hart::Reg, rs1: Hart::Reg },
21    Sha256Sig1 { rd: Hart::Reg, rs1: Hart::Reg },
22    Sha256Sum0 { rd: Hart::Reg, rs1: Hart::Reg },
23    Sha256Sum1 { rd: Hart::Reg, rs1: Hart::Reg },
24    Sha512Sig0 { rd: Hart::Reg, rs1: Hart::Reg },
25    Sha512Sig1 { rd: Hart::Reg, rs1: Hart::Reg },
26    Sha512Sum0 { rd: Hart::Reg, rs1: Hart::Reg },
27    Sha512Sum1 { rd: Hart::Reg, rs1: Hart::Reg },
28}
29
30#[instruction]
31const impl<Reg, Hart> Instruction for Rv64ZknhInstruction<Hart>
32where
33    Reg: [const] Register<Type = u64>,
34    Hart: [const] HartConfig<Reg = Reg>,
35{
36    const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = &[IsaExtension::new("zknh", 1, 0)];
37
38    const ALIGNMENT: u8 = align_of::<u32>() as u8;
39
40    type Hart = Hart;
41
42    #[inline(always)]
43    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
44    fn try_decode(instruction: u32) -> Option<Self> {
45        let opcode = (instruction & 0b111_1111) as u8;
46        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
47        let funct3 = ((instruction >> 12) & 0b111) as u8;
48        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
49        let funct5 = ((instruction >> 20) & 0x1f) as u8;
50        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
51
52        match opcode {
53            // I-type format (OP-IMM encoding)
54            0b001_0011 => {
55                if funct3 != 0b001 || funct7 != 0b000_1000 {
56                    None
57                } else {
58                    let rd = Reg::from_bits(rd_bits)?;
59                    let rs1 = Reg::from_bits(rs1_bits)?;
60                    match funct5 {
61                        // SHA-256 instructions
62                        0b0_0010 => Some(Self::Sha256Sig0 { rd, rs1 }),
63                        0b0_0011 => Some(Self::Sha256Sig1 { rd, rs1 }),
64                        0b0_0000 => Some(Self::Sha256Sum0 { rd, rs1 }),
65                        0b0_0001 => Some(Self::Sha256Sum1 { rd, rs1 }),
66                        // SHA-512 instructions
67                        0b0_0110 => Some(Self::Sha512Sig0 { rd, rs1 }),
68                        0b0_0111 => Some(Self::Sha512Sig1 { rd, rs1 }),
69                        0b0_0100 => Some(Self::Sha512Sum0 { rd, rs1 }),
70                        0b0_0101 => Some(Self::Sha512Sum1 { rd, rs1 }),
71                        _ => None,
72                    }
73                }
74            }
75            _ => None,
76        }
77    }
78
79    #[inline(always)]
80    fn size(&self) -> u8 {
81        size_of::<u32>() as u8
82    }
83}
84
85#[instruction]
86impl<Reg, Hart> fmt::Display for Rv64ZknhInstruction<Hart>
87where
88    Reg: fmt::Display,
89    Hart: HartConfig<Reg = Reg>,
90{
91    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
92        match self {
93            Self::Sha256Sig0 { rd, rs1 } => write!(f, "sha256sig0 {rd}, {rs1}"),
94            Self::Sha256Sig1 { rd, rs1 } => write!(f, "sha256sig1 {rd}, {rs1}"),
95            Self::Sha256Sum0 { rd, rs1 } => write!(f, "sha256sum0 {rd}, {rs1}"),
96            Self::Sha256Sum1 { rd, rs1 } => write!(f, "sha256sum1 {rd}, {rs1}"),
97            Self::Sha512Sig0 { rd, rs1 } => write!(f, "sha512sig0 {rd}, {rs1}"),
98            Self::Sha512Sig1 { rd, rs1 } => write!(f, "sha512sig1 {rd}, {rs1}"),
99            Self::Sha512Sum0 { rd, rs1 } => write!(f, "sha512sum0 {rd}, {rs1}"),
100            Self::Sha512Sum1 { rd, rs1 } => write!(f, "sha512sum1 {rd}, {rs1}"),
101        }
102    }
103}
ab_riscv_primitives/instructions/rv64/zk/zkn/zknh.rs

ab_riscv_primitives/instructions/rv64/zk/zkn/
zknh.rs
