ab_riscv_primitives/instructions/rv64/zk/zkn/
zknh.rs

1//! RV64 Zknh extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11/// RISC-V RV64 Zknh instruction (SHA-256 and SHA-512 sigma functions)
12#[instruction]
13#[derive(Debug, Clone, Copy, PartialEq, Eq)]
14pub enum Rv64ZknhInstruction<Reg> {
15    Sha256Sig0 { rd: Reg, rs1: Reg },
16    Sha256Sig1 { rd: Reg, rs1: Reg },
17    Sha256Sum0 { rd: Reg, rs1: Reg },
18    Sha256Sum1 { rd: Reg, rs1: Reg },
19    Sha512Sig0 { rd: Reg, rs1: Reg },
20    Sha512Sig1 { rd: Reg, rs1: Reg },
21    Sha512Sum0 { rd: Reg, rs1: Reg },
22    Sha512Sum1 { rd: Reg, rs1: Reg },
23}
24
25#[instruction]
26const impl<Reg> Instruction for Rv64ZknhInstruction<Reg>
27where
28    Reg: [const] Register<Type = u64>,
29{
30    type Reg = Reg;
31
32    #[inline(always)]
33    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
34    fn try_decode(instruction: u32) -> Option<Self> {
35        let opcode = (instruction & 0b111_1111) as u8;
36        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
37        let funct3 = ((instruction >> 12) & 0b111) as u8;
38        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
39        let funct5 = ((instruction >> 20) & 0x1f) as u8;
40        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
41
42        match opcode {
43            // I-type format (OP-IMM encoding)
44            0b001_0011 => {
45                if funct3 != 0b001 || funct7 != 0b000_1000 {
46                    None
47                } else {
48                    let rd = Reg::from_bits(rd_bits)?;
49                    let rs1 = Reg::from_bits(rs1_bits)?;
50                    match funct5 {
51                        // SHA-256 instructions
52                        0b0_0010 => Some(Self::Sha256Sig0 { rd, rs1 }),
53                        0b0_0011 => Some(Self::Sha256Sig1 { rd, rs1 }),
54                        0b0_0000 => Some(Self::Sha256Sum0 { rd, rs1 }),
55                        0b0_0001 => Some(Self::Sha256Sum1 { rd, rs1 }),
56                        // SHA-512 instructions
57                        0b0_0110 => Some(Self::Sha512Sig0 { rd, rs1 }),
58                        0b0_0111 => Some(Self::Sha512Sig1 { rd, rs1 }),
59                        0b0_0100 => Some(Self::Sha512Sum0 { rd, rs1 }),
60                        0b0_0101 => Some(Self::Sha512Sum1 { rd, rs1 }),
61                        _ => None,
62                    }
63                }
64            }
65            _ => None,
66        }
67    }
68
69    #[inline(always)]
70    fn alignment() -> u8 {
71        align_of::<u32>() as u8
72    }
73
74    #[inline(always)]
75    fn size(&self) -> u8 {
76        size_of::<u32>() as u8
77    }
78}
79
80#[instruction]
81impl<Reg> fmt::Display for Rv64ZknhInstruction<Reg>
82where
83    Reg: fmt::Display,
84{
85    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
86        match self {
87            Self::Sha256Sig0 { rd, rs1 } => write!(f, "sha256sig0 {rd}, {rs1}"),
88            Self::Sha256Sig1 { rd, rs1 } => write!(f, "sha256sig1 {rd}, {rs1}"),
89            Self::Sha256Sum0 { rd, rs1 } => write!(f, "sha256sum0 {rd}, {rs1}"),
90            Self::Sha256Sum1 { rd, rs1 } => write!(f, "sha256sum1 {rd}, {rs1}"),
91            Self::Sha512Sig0 { rd, rs1 } => write!(f, "sha512sig0 {rd}, {rs1}"),
92            Self::Sha512Sig1 { rd, rs1 } => write!(f, "sha512sig1 {rd}, {rs1}"),
93            Self::Sha512Sum0 { rd, rs1 } => write!(f, "sha512sum0 {rd}, {rs1}"),
94            Self::Sha512Sum1 { rd, rs1 } => write!(f, "sha512sum1 {rd}, {rs1}"),
95        }
96    }
97}
ab_riscv_primitives/instructions/rv64/zk/zkn/zknh.rs

ab_riscv_primitives/instructions/rv64/zk/zkn/
zknh.rs
