ab_riscv_primitives/instructions/rv64/zk/zkn/
zknh.rs

1//! RV64 Zknh extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11/// RISC-V RV64 Zknh instruction (SHA-256 and SHA-512 sigma functions)
12#[instruction]
13#[derive(Debug, Clone, Copy)]
14#[derive_const(PartialEq, Eq)]
15pub enum Rv64ZknhInstruction<Reg> {
16    Sha256Sig0 { rd: Reg, rs1: Reg },
17    Sha256Sig1 { rd: Reg, rs1: Reg },
18    Sha256Sum0 { rd: Reg, rs1: Reg },
19    Sha256Sum1 { rd: Reg, rs1: Reg },
20    Sha512Sig0 { rd: Reg, rs1: Reg },
21    Sha512Sig1 { rd: Reg, rs1: Reg },
22    Sha512Sum0 { rd: Reg, rs1: Reg },
23    Sha512Sum1 { rd: Reg, rs1: Reg },
24}
25
26#[instruction]
27const impl<Reg> Instruction for Rv64ZknhInstruction<Reg>
28where
29    Reg: [const] Register<Type = u64>,
30{
31    type Reg = Reg;
32
33    #[inline(always)]
34    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
35    fn try_decode(instruction: u32) -> Option<Self> {
36        let opcode = (instruction & 0b111_1111) as u8;
37        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
38        let funct3 = ((instruction >> 12) & 0b111) as u8;
39        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
40        let funct5 = ((instruction >> 20) & 0x1f) as u8;
41        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
42
43        match opcode {
44            // I-type format (OP-IMM encoding)
45            0b001_0011 => {
46                if funct3 != 0b001 || funct7 != 0b000_1000 {
47                    None
48                } else {
49                    let rd = Reg::from_bits(rd_bits)?;
50                    let rs1 = Reg::from_bits(rs1_bits)?;
51                    match funct5 {
52                        // SHA-256 instructions
53                        0b0_0010 => Some(Self::Sha256Sig0 { rd, rs1 }),
54                        0b0_0011 => Some(Self::Sha256Sig1 { rd, rs1 }),
55                        0b0_0000 => Some(Self::Sha256Sum0 { rd, rs1 }),
56                        0b0_0001 => Some(Self::Sha256Sum1 { rd, rs1 }),
57                        // SHA-512 instructions
58                        0b0_0110 => Some(Self::Sha512Sig0 { rd, rs1 }),
59                        0b0_0111 => Some(Self::Sha512Sig1 { rd, rs1 }),
60                        0b0_0100 => Some(Self::Sha512Sum0 { rd, rs1 }),
61                        0b0_0101 => Some(Self::Sha512Sum1 { rd, rs1 }),
62                        _ => None,
63                    }
64                }
65            }
66            _ => None,
67        }
68    }
69
70    #[inline(always)]
71    fn alignment() -> u8 {
72        align_of::<u32>() as u8
73    }
74
75    #[inline(always)]
76    fn size(&self) -> u8 {
77        size_of::<u32>() as u8
78    }
79}
80
81#[instruction]
82impl<Reg> fmt::Display for Rv64ZknhInstruction<Reg>
83where
84    Reg: fmt::Display,
85{
86    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
87        match self {
88            Self::Sha256Sig0 { rd, rs1 } => write!(f, "sha256sig0 {rd}, {rs1}"),
89            Self::Sha256Sig1 { rd, rs1 } => write!(f, "sha256sig1 {rd}, {rs1}"),
90            Self::Sha256Sum0 { rd, rs1 } => write!(f, "sha256sum0 {rd}, {rs1}"),
91            Self::Sha256Sum1 { rd, rs1 } => write!(f, "sha256sum1 {rd}, {rs1}"),
92            Self::Sha512Sig0 { rd, rs1 } => write!(f, "sha512sig0 {rd}, {rs1}"),
93            Self::Sha512Sig1 { rd, rs1 } => write!(f, "sha512sig1 {rd}, {rs1}"),
94            Self::Sha512Sum0 { rd, rs1 } => write!(f, "sha512sum0 {rd}, {rs1}"),
95            Self::Sha512Sum1 { rd, rs1 } => write!(f, "sha512sum1 {rd}, {rs1}"),
96        }
97    }
98}
ab_riscv_primitives/instructions/rv64/zk/zkn/zknh.rs

ab_riscv_primitives/instructions/rv64/zk/zkn/
zknh.rs
