ab_riscv_primitives/instructions/rv64/zk/zkn/
zkne.rs

1//! RV64 Zkne extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::hart::HartConfig;
7use crate::instructions::rv64::zk::zkn::zknd::{Rv64ZkndKsRnum, Rv64ZkndZkneSharedInstruction};
8use crate::instructions::{ImplementedExtension, Instruction, IsaExtension};
9use crate::registers::general_purpose::Register;
10use ab_riscv_macros::instruction;
11use core::fmt;
12
13/// RISC-V RV64 Zkne instructions
14#[instruction(
15    reorder = [Aes64Es, Aes64Esm],
16    inherit = [Rv64ZkndZkneSharedInstruction],
17)]
18#[derive(Debug, Clone, Copy)]
19#[derive_const(PartialEq, Eq)]
20#[rustfmt::skip]
21pub enum Rv64ZkneInstruction<Hart>
22where
23    Hart: HartConfig,
24{
25    /// AES final round encryption: ShiftRows + SubBytes, no MixColumns
26    Aes64Es { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
27    /// AES middle round encryption: ShiftRows + SubBytes + MixColumns
28    Aes64Esm { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
29}
30
31#[instruction]
32const impl<Reg, Hart> Instruction for Rv64ZkneInstruction<Hart>
33where
34    Reg: [const] Register<Type = u64>,
35    Hart: [const] HartConfig<Reg = Reg>,
36{
37    const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = &[IsaExtension::new("zkne", 1, 0)];
38
39    const ALIGNMENT: u8 = align_of::<u32>() as u8;
40
41    type Hart = Hart;
42
43    #[inline(always)]
44    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
45    fn try_decode(instruction: u32) -> Option<Self> {
46        let opcode = (instruction & 0b111_1111) as u8;
47        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
48        let funct3 = ((instruction >> 12) & 0b111) as u8;
49        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
50        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
51        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
52
53        // R-type: OP opcode (0x33)
54        //   aes64es:  funct7=0b001_1001, funct3=0 -> MATCH=0x3200_0033
55        //   aes64esm: funct7=0b001_1011, funct3=0 -> MATCH=0x3600_0033
56        match opcode {
57            0b011_0011 => {
58                if funct3 != 0b000 {
59                    None?;
60                }
61                let rd = Reg::from_bits(rd_bits)?;
62                let rs1 = Reg::from_bits(rs1_bits)?;
63                let rs2 = Reg::from_bits(rs2_bits)?;
64                match funct7 {
65                    0b001_1001 => Some(Self::Aes64Es { rd, rs1, rs2 }),
66                    0b001_1011 => Some(Self::Aes64Esm { rd, rs1, rs2 }),
67                    _ => None,
68                }
69            }
70            _ => None,
71        }
72    }
73
74    #[inline(always)]
75    fn size(&self) -> u8 {
76        size_of::<u32>() as u8
77    }
78}
79
80#[instruction]
81impl<Reg, Hart> fmt::Display for Rv64ZkneInstruction<Hart>
82where
83    Reg: fmt::Display + Copy,
84    Hart: HartConfig<Reg = Reg>,
85{
86    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
87        match self {
88            Self::Aes64Es { rd: rd1, rs1, rs2 } => write!(f, "aes64es {rd1}, {rs1}, {rs2}"),
89            Self::Aes64Esm { rd, rs1, rs2 } => write!(f, "aes64esm {rd}, {rs1}, {rs2}"),
90        }
91    }
92}
ab_riscv_primitives/instructions/rv64/zk/zkn/zkne.rs

ab_riscv_primitives/instructions/rv64/zk/zkn/
zkne.rs
