ab_riscv_primitives/instructions/rv64/zk/zkn/
zkne.rs

1//! RV64 Zkne extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::instructions::rv64::zk::zkn::zknd::{Rv64ZkndInstruction, Rv64ZkndKsRnum};
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12/// RISC-V RV64 Zkne instructions
13#[instruction(
14    reorder = [Aes64Es, Aes64Esm, Aes64Ks1i, Aes64Ks2],
15    ignore = [Rv64ZkndInstruction],
16    inherit = [Rv64ZkndInstruction],
17)]
18#[derive(Debug, Clone, Copy, PartialEq, Eq)]
19pub enum Rv64ZkneInstruction<Reg> {
20    /// AES final round encryption: ShiftRows + SubBytes, no MixColumns
21    Aes64Es { rd: Reg, rs1: Reg, rs2: Reg },
22    /// AES middle round encryption: ShiftRows + SubBytes + MixColumns
23    Aes64Esm { rd: Reg, rs1: Reg, rs2: Reg },
24}
25
26#[instruction]
27const impl<Reg> Instruction for Rv64ZkneInstruction<Reg>
28where
29    Reg: [const] Register<Type = u64>,
30{
31    type Reg = Reg;
32
33    #[inline(always)]
34    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
35    fn try_decode(instruction: u32) -> Option<Self> {
36        let opcode = (instruction & 0b111_1111) as u8;
37        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
38        let funct3 = ((instruction >> 12) & 0b111) as u8;
39        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
40        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
41        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
42
43        // R-type: OP opcode (0x33)
44        //   aes64es:  funct7=0b001_1001, funct3=0 -> MATCH=0x3200_0033
45        //   aes64esm: funct7=0b001_1011, funct3=0 -> MATCH=0x3600_0033
46        match opcode {
47            0b011_0011 => {
48                if funct3 != 0b000 {
49                    None?;
50                }
51                let rd = Reg::from_bits(rd_bits)?;
52                let rs1 = Reg::from_bits(rs1_bits)?;
53                let rs2 = Reg::from_bits(rs2_bits)?;
54                match funct7 {
55                    0b001_1001 => Some(Self::Aes64Es { rd, rs1, rs2 }),
56                    0b001_1011 => Some(Self::Aes64Esm { rd, rs1, rs2 }),
57                    _ => None,
58                }
59            }
60            _ => None,
61        }
62    }
63
64    #[inline(always)]
65    fn alignment() -> u8 {
66        align_of::<u32>() as u8
67    }
68
69    #[inline(always)]
70    fn size(&self) -> u8 {
71        size_of::<u32>() as u8
72    }
73}
74
75#[instruction]
76impl<Reg> fmt::Display for Rv64ZkneInstruction<Reg>
77where
78    Reg: fmt::Display + Copy,
79{
80    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
81        match self {
82            Self::Aes64Es {
83                rd: rd1, rs1, rs2, ..
84            } => write!(f, "aes64es {rd1}, {rs1}, {rs2}"),
85            Self::Aes64Esm { rd, rs1, rs2 } => write!(f, "aes64esm {rd}, {rs1}, {rs2}"),
86        }
87    }
88}
ab_riscv_primitives/instructions/rv64/zk/zkn/zkne.rs

ab_riscv_primitives/instructions/rv64/zk/zkn/
zkne.rs
