ab_riscv_primitives/instructions/rv64/zk/zkn/
zkne.rs

1//! RV64 Zkne extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::instructions::rv64::zk::zkn::zknd::{Rv64ZkndInstruction, Rv64ZkndKsRnum};
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12/// RISC-V RV64 Zkne instructions
13#[instruction(
14    reorder = [Aes64Es, Aes64Esm, Aes64Ks1i, Aes64Ks2],
15    ignore = [Rv64ZkndInstruction],
16    inherit = [Rv64ZkndInstruction],
17)]
18#[derive(Debug, Clone, Copy, PartialEq, Eq)]
19pub enum Rv64ZkneInstruction<Reg> {
20    /// AES final round encryption: ShiftRows + SubBytes, no MixColumns
21    Aes64Es { rd: Reg, rs1: Reg, rs2: Reg },
22    /// AES middle round encryption: ShiftRows + SubBytes + MixColumns
23    Aes64Esm { rd: Reg, rs1: Reg, rs2: Reg },
24}
25
26#[instruction]
27impl<Reg> const Instruction for Rv64ZkneInstruction<Reg>
28where
29    Reg: [const] Register<Type = u64>,
30{
31    type Reg = Reg;
32
33    #[inline(always)]
34    fn try_decode(instruction: u32) -> Option<Self> {
35        let opcode = (instruction & 0b111_1111) as u8;
36        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
37        let funct3 = ((instruction >> 12) & 0b111) as u8;
38        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
39        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
40        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
41
42        // R-type: OP opcode (0x33)
43        //   aes64es:  funct7=0b0011001, funct3=0 -> MATCH=0x32000033
44        //   aes64esm: funct7=0b0011011, funct3=0 -> MATCH=0x36000033
45        match opcode {
46            0b0110011 => {
47                if funct3 != 0b000 {
48                    None?;
49                }
50                let rd = Reg::from_bits(rd_bits)?;
51                let rs1 = Reg::from_bits(rs1_bits)?;
52                let rs2 = Reg::from_bits(rs2_bits)?;
53                match funct7 {
54                    0b0011001 => Some(Self::Aes64Es { rd, rs1, rs2 }),
55                    0b0011011 => Some(Self::Aes64Esm { rd, rs1, rs2 }),
56                    _ => None,
57                }
58            }
59            _ => None,
60        }
61    }
62
63    #[inline(always)]
64    fn alignment() -> u8 {
65        align_of::<u32>() as u8
66    }
67
68    #[inline(always)]
69    fn size(&self) -> u8 {
70        size_of::<u32>() as u8
71    }
72}
73
74#[instruction]
75impl<Reg> fmt::Display for Rv64ZkneInstruction<Reg>
76where
77    Reg: fmt::Display + Copy,
78{
79    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
80        match self {
81            Self::Aes64Es { rd, rs1, rs2 } => write!(f, "aes64es {rd}, {rs1}, {rs2}"),
82            Self::Aes64Esm { rd, rs1, rs2 } => write!(f, "aes64esm {rd}, {rs1}, {rs2}"),
83        }
84    }
85}
ab_riscv_primitives/instructions/rv64/zk/zkn/zkne.rs

ab_riscv_primitives/instructions/rv64/zk/zkn/
zkne.rs
