ab_riscv_primitives/instructions/rv64/zk/
zkn.rs

1//! RV64 Zkn extension
2
3pub mod zknd;
4pub mod zkne;
5pub mod zknh;
6
7use crate::instructions::Instruction;
8use crate::instructions::rv64::b::zbb::Rv64ZbbInstruction;
9use crate::instructions::rv64::b::zbc::Rv64ZbcInstruction;
10use crate::instructions::rv64::zk::zbkb::Rv64ZbkbInstruction;
11use crate::instructions::rv64::zk::zbkc::Rv64ZbkcInstruction;
12use crate::instructions::rv64::zk::zbkx::Rv64ZbkxInstruction;
13use crate::instructions::rv64::zk::zkn::zknd::{Rv64ZkndInstruction, Rv64ZkndKsRnum};
14use crate::instructions::rv64::zk::zkn::zkne::Rv64ZkneInstruction;
15use crate::instructions::rv64::zk::zkn::zknh::Rv64ZknhInstruction;
16use crate::registers::general_purpose::Register;
17use ab_riscv_macros::instruction;
18use core::fmt;
19
20/// RISC-V RV64 Zkn (Zbkb + Zbkc + Zbkx + Zknd + Zkne + Zknh) instruction
21#[instruction(
22    inherit = [
23        Rv64ZbkbInstruction,
24        Rv64ZbkcInstruction,
25        Rv64ZbkxInstruction,
26        Rv64ZkndInstruction,
27        Rv64ZkneInstruction,
28        Rv64ZknhInstruction,
29    ]
30)]
31#[derive(Debug, Clone, Copy)]
32#[derive_const(PartialEq, Eq)]
33pub enum Rv64ZknInstruction<Reg> {}
34
35#[instruction]
36const impl<Reg> Instruction for Rv64ZknInstruction<Reg>
37where
38    Reg: [const] Register<Type = u64>,
39{
40    const ALIGNMENT: u8 = align_of::<u32>() as u8;
41
42    type Reg = Reg;
43
44    #[inline(always)]
45    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
46    fn try_decode(instruction: u32) -> Option<Self> {
47        None
48    }
49
50    #[inline(always)]
51    fn size(&self) -> u8 {
52        size_of::<u32>() as u8
53    }
54}
55
56#[instruction]
57impl<Reg> fmt::Display for Rv64ZknInstruction<Reg>
58where
59    Reg: fmt::Display + Copy,
60{
61    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
62        match self {}
63    }
64}
ab_riscv_primitives/instructions/rv64/zk/zkn.rs

ab_riscv_primitives/instructions/rv64/zk/
zkn.rs
