ab_riscv_primitives/instructions/rv64/zk/
zbkx.rs1#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11#[instruction]
13#[derive(Debug, Clone, Copy, PartialEq, Eq)]
14pub enum Rv64ZbkxInstruction<Reg> {
15 Xperm4 { rd: Reg, rs1: Reg, rs2: Reg },
16 Xperm8 { rd: Reg, rs1: Reg, rs2: Reg },
17}
18
19#[instruction]
20impl<Reg> const Instruction for Rv64ZbkxInstruction<Reg>
21where
22 Reg: [const] Register<Type = u64>,
23{
24 type Reg = Reg;
25
26 #[inline(always)]
27 fn try_decode(instruction: u32) -> Option<Self> {
28 let opcode = (instruction & 0b111_1111) as u8;
29 let rd_bits = ((instruction >> 7) & 0x1f) as u8;
30 let funct3 = ((instruction >> 12) & 0b111) as u8;
31 let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
32 let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
33 let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
34
35 match opcode {
36 0b0110011 => {
37 let rd = Reg::from_bits(rd_bits)?;
38 let rs1 = Reg::from_bits(rs1_bits)?;
39 let rs2 = Reg::from_bits(rs2_bits)?;
40 match (funct3, funct7) {
41 (0b010, 0b0010100) => Some(Self::Xperm4 { rd, rs1, rs2 }),
42 (0b100, 0b0010100) => Some(Self::Xperm8 { rd, rs1, rs2 }),
43 _ => None,
44 }
45 }
46 _ => None,
47 }
48 }
49
50 #[inline(always)]
51 fn alignment() -> u8 {
52 align_of::<u32>() as u8
53 }
54
55 #[inline(always)]
56 fn size(&self) -> u8 {
57 size_of::<u32>() as u8
58 }
59}
60
61impl<Reg> fmt::Display for Rv64ZbkxInstruction<Reg>
62where
63 Reg: fmt::Display,
64{
65 fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
66 match self {
67 Self::Xperm4 { rd, rs1, rs2 } => write!(f, "xperm4 {}, {}, {}", rd, rs1, rs2),
68 Self::Xperm8 { rd, rs1, rs2 } => write!(f, "xperm8 {}, {}, {}", rd, rs1, rs2),
69 }
70 }
71}