ab_riscv_primitives/instructions/rv64/zk/
zbkx.rs1#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11#[instruction]
13#[derive(Debug, Clone, Copy)]
14#[derive_const(PartialEq, Eq)]
15pub enum Rv64ZbkxInstruction<Reg> {
16 Xperm4 { rd: Reg, rs1: Reg, rs2: Reg },
17 Xperm8 { rd: Reg, rs1: Reg, rs2: Reg },
18}
19
20#[instruction]
21const impl<Reg> Instruction for Rv64ZbkxInstruction<Reg>
22where
23 Reg: [const] Register<Type = u64>,
24{
25 type Reg = Reg;
26
27 #[inline(always)]
28 #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
29 fn try_decode(instruction: u32) -> Option<Self> {
30 let opcode = (instruction & 0b111_1111) as u8;
31 let rd_bits = ((instruction >> 7) & 0x1f) as u8;
32 let funct3 = ((instruction >> 12) & 0b111) as u8;
33 let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
34 let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
35 let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
36
37 match opcode {
38 0b011_0011 => {
39 let rd = Reg::from_bits(rd_bits)?;
40 let rs1 = Reg::from_bits(rs1_bits)?;
41 let rs2 = Reg::from_bits(rs2_bits)?;
42 match (funct3, funct7) {
43 (0b010, 0b001_0100) => Some(Self::Xperm4 { rd, rs1, rs2 }),
44 (0b100, 0b001_0100) => Some(Self::Xperm8 { rd, rs1, rs2 }),
45 _ => None,
46 }
47 }
48 _ => None,
49 }
50 }
51
52 #[inline(always)]
53 fn alignment() -> u8 {
54 align_of::<u32>() as u8
55 }
56
57 #[inline(always)]
58 fn size(&self) -> u8 {
59 size_of::<u32>() as u8
60 }
61}
62
63#[instruction]
64impl<Reg> fmt::Display for Rv64ZbkxInstruction<Reg>
65where
66 Reg: fmt::Display,
67{
68 fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
69 match self {
70 Self::Xperm4 { rd, rs1, rs2 } => write!(f, "xperm4 {rd}, {rs1}, {rs2}"),
71 Self::Xperm8 { rd, rs1, rs2 } => write!(f, "xperm8 {rd}, {rs1}, {rs2}"),
72 }
73 }
74}