ab_riscv_primitives/instructions/rv64/zk/
zbkx.rs1#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11#[instruction]
13#[derive(Debug, Clone, Copy)]
14#[derive_const(PartialEq, Eq)]
15pub enum Rv64ZbkxInstruction<Reg> {
16 Xperm4 { rd: Reg, rs1: Reg, rs2: Reg },
17 Xperm8 { rd: Reg, rs1: Reg, rs2: Reg },
18}
19
20#[instruction]
21const impl<Reg> Instruction for Rv64ZbkxInstruction<Reg>
22where
23 Reg: [const] Register<Type = u64>,
24{
25 const ALIGNMENT: u8 = align_of::<u32>() as u8;
26
27 type Reg = Reg;
28
29 #[inline(always)]
30 #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
31 fn try_decode(instruction: u32) -> Option<Self> {
32 let opcode = (instruction & 0b111_1111) as u8;
33 let rd_bits = ((instruction >> 7) & 0x1f) as u8;
34 let funct3 = ((instruction >> 12) & 0b111) as u8;
35 let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
36 let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
37 let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
38
39 match opcode {
40 0b011_0011 => {
41 let rd = Reg::from_bits(rd_bits)?;
42 let rs1 = Reg::from_bits(rs1_bits)?;
43 let rs2 = Reg::from_bits(rs2_bits)?;
44 match (funct3, funct7) {
45 (0b010, 0b001_0100) => Some(Self::Xperm4 { rd, rs1, rs2 }),
46 (0b100, 0b001_0100) => Some(Self::Xperm8 { rd, rs1, rs2 }),
47 _ => None,
48 }
49 }
50 _ => None,
51 }
52 }
53
54 #[inline(always)]
55 fn size(&self) -> u8 {
56 size_of::<u32>() as u8
57 }
58}
59
60#[instruction]
61impl<Reg> fmt::Display for Rv64ZbkxInstruction<Reg>
62where
63 Reg: fmt::Display,
64{
65 fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
66 match self {
67 Self::Xperm4 { rd, rs1, rs2 } => write!(f, "xperm4 {rd}, {rs1}, {rs2}"),
68 Self::Xperm8 { rd, rs1, rs2 } => write!(f, "xperm8 {rd}, {rs1}, {rs2}"),
69 }
70 }
71}