ab_riscv_primitives/instructions/rv64/zk/
zbkc.rs

1//! RV64 Zbkc extension (subset of Zbc extension)
2
3#[cfg(test)]
4mod tests;
5
6use crate::hart::HartConfig;
7use crate::instructions::{ImplementedExtension, Instruction, IsaExtension};
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12/// RISC-V RV64 Zbkc instruction
13#[instruction]
14#[derive(Debug, Clone, Copy)]
15#[derive_const(PartialEq, Eq)]
16#[rustfmt::skip]
17pub enum Rv64ZbkcInstruction<Hart>
18where
19    Hart: HartConfig,
20{
21    Clmul { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
22    Clmulh { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
23}
24
25#[instruction]
26const impl<Reg, Hart> Instruction for Rv64ZbkcInstruction<Hart>
27where
28    Reg: [const] Register<Type = u64>,
29    Hart: [const] HartConfig<Reg = Reg>,
30{
31    const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = &[IsaExtension::new("zbkc", 1, 0)];
32
33    const ALIGNMENT: u8 = align_of::<u32>() as u8;
34
35    type Hart = Hart;
36
37    #[inline(always)]
38    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
39    fn try_decode(instruction: u32) -> Option<Self> {
40        let opcode = (instruction & 0b111_1111) as u8;
41        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
42        let funct3 = ((instruction >> 12) & 0b111) as u8;
43        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
44        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
45        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
46
47        match opcode {
48            // R-type
49            0b011_0011 => {
50                let rd = Reg::from_bits(rd_bits)?;
51                let rs1 = Reg::from_bits(rs1_bits)?;
52                let rs2 = Reg::from_bits(rs2_bits)?;
53                match (funct3, funct7) {
54                    (0b001, 0b000_0101) => Some(Self::Clmul { rd, rs1, rs2 }),
55                    (0b011, 0b000_0101) => Some(Self::Clmulh { rd, rs1, rs2 }),
56                    _ => None,
57                }
58            }
59            _ => None,
60        }
61    }
62
63    #[inline(always)]
64    fn size(&self) -> u8 {
65        size_of::<u32>() as u8
66    }
67}
68
69#[instruction]
70impl<Reg, Hart> fmt::Display for Rv64ZbkcInstruction<Hart>
71where
72    Reg: fmt::Display,
73    Hart: HartConfig<Reg = Reg>,
74{
75    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
76        match self {
77            Self::Clmul { rd, rs1, rs2 } => write!(f, "clmul {rd}, {rs1}, {rs2}"),
78            Self::Clmulh { rd, rs1, rs2 } => write!(f, "clmulh {rd}, {rs1}, {rs2}"),
79        }
80    }
81}
ab_riscv_primitives/instructions/rv64/zk/zbkc.rs

ab_riscv_primitives/instructions/rv64/zk/
zbkc.rs
