ab_riscv_primitives/instructions/rv64/
zicsr.rs

1//! RV64 Zicsr extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11/// RISC-V RV64 Zicsr instruction (Control and Status Register)
12#[instruction]
13#[derive(Debug, Clone, Copy, PartialEq, Eq)]
14pub enum Rv64ZicsrInstruction<Reg> {
15    Csrrw { rd: Reg, rs1: Reg, csr: u16 },
16    Csrrs { rd: Reg, rs1: Reg, csr: u16 },
17    Csrrc { rd: Reg, rs1: Reg, csr: u16 },
18    Csrrwi { rd: Reg, zimm: u8, csr: u16 },
19    Csrrsi { rd: Reg, zimm: u8, csr: u16 },
20    Csrrci { rd: Reg, zimm: u8, csr: u16 },
21}
22
23#[instruction]
24impl<Reg> const Instruction for Rv64ZicsrInstruction<Reg>
25where
26    Reg: [const] Register,
27{
28    type Reg = Reg;
29
30    #[inline(always)]
31    fn try_decode(instruction: u32) -> Option<Self> {
32        let opcode = (instruction & 0b111_1111) as u8;
33        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
34        let funct3 = ((instruction >> 12) & 0b111) as u8;
35        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
36        let csr_bits = ((instruction >> 20) & 0x0fff) as u16;
37
38        match opcode {
39            0b1110011 => {
40                let rd = Reg::from_bits(rd_bits)?;
41                match funct3 {
42                    0b001 => {
43                        let rs1 = Reg::from_bits(rs1_bits)?;
44                        Some(Self::Csrrw {
45                            rd,
46                            rs1,
47                            csr: csr_bits,
48                        })
49                    }
50                    0b010 => {
51                        let rs1 = Reg::from_bits(rs1_bits)?;
52                        Some(Self::Csrrs {
53                            rd,
54                            rs1,
55                            csr: csr_bits,
56                        })
57                    }
58                    0b011 => {
59                        let rs1 = Reg::from_bits(rs1_bits)?;
60                        Some(Self::Csrrc {
61                            rd,
62                            rs1,
63                            csr: csr_bits,
64                        })
65                    }
66                    0b101 => Some(Self::Csrrwi {
67                        rd,
68                        zimm: rs1_bits,
69                        csr: csr_bits,
70                    }),
71                    0b110 => Some(Self::Csrrsi {
72                        rd,
73                        zimm: rs1_bits,
74                        csr: csr_bits,
75                    }),
76                    0b111 => Some(Self::Csrrci {
77                        rd,
78                        zimm: rs1_bits,
79                        csr: csr_bits,
80                    }),
81                    _ => None,
82                }
83            }
84            _ => None,
85        }
86    }
87
88    #[inline(always)]
89    fn alignment() -> u8 {
90        size_of::<u32>() as u8
91    }
92
93    #[inline(always)]
94    fn size(&self) -> u8 {
95        size_of::<u32>() as u8
96    }
97}
98
99impl<Reg> fmt::Display for Rv64ZicsrInstruction<Reg>
100where
101    Reg: fmt::Display,
102{
103    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
104        match self {
105            Self::Csrrw { rd, rs1, csr } => write!(f, "csrrw {rd}, {csr}, {rs1}"),
106            Self::Csrrs { rd, rs1, csr } => write!(f, "csrrs {rd}, {csr}, {rs1}"),
107            Self::Csrrc { rd, rs1, csr } => write!(f, "csrrc {rd}, {csr}, {rs1}"),
108            Self::Csrrwi { rd, zimm, csr } => write!(f, "csrrwi {rd}, {csr}, {zimm}"),
109            Self::Csrrsi { rd, zimm, csr } => write!(f, "csrrsi {rd}, {csr}, {zimm}"),
110            Self::Csrrci { rd, zimm, csr } => write!(f, "csrrci {rd}, {csr}, {zimm}"),
111        }
112    }
113}
ab_riscv_primitives/instructions/rv64/zicsr.rs

ab_riscv_primitives/instructions/rv64/
zicsr.rs
