ab_riscv_primitives/instructions/rv64/zce/
zcb.rs

1//! RV64 Zcb extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::instructions::rv64::c::zca::Rv64ZcaInstruction;
8use crate::instructions::utils::I24;
9use crate::registers::general_purpose::Register;
10use ab_riscv_macros::instruction;
11use core::fmt;
12
13/// RISC-V RV64 Zcb compressed instruction set.
14///
15/// All register operands are prime-field (x8–x15) registers.
16#[instruction(
17    inherit = [Rv64ZcaInstruction, Rv64ZcbOnlyInstruction],
18)]
19#[derive(Debug, Clone, Copy)]
20#[derive_const(PartialEq, Eq)]
21pub enum Rv64ZcbInstruction<Reg> {}
22
23#[instruction]
24const impl<Reg> Instruction for Rv64ZcbInstruction<Reg>
25where
26    Reg: [const] Register<Type = u64>,
27{
28    const ALIGNMENT: u8 = align_of::<u16>() as u8;
29
30    type Reg = Reg;
31
32    #[inline(always)]
33    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
34    fn try_decode(instruction: u32) -> Option<Self> {
35        None
36    }
37
38    #[inline(always)]
39    fn size(&self) -> u8 {
40        size_of::<u16>() as u8
41    }
42}
43
44#[instruction]
45impl<Reg> fmt::Display for Rv64ZcbInstruction<Reg>
46where
47    Reg: fmt::Display + Copy,
48{
49    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
50        match self {}
51    }
52}
53
54/// Instruction that contains isolated Zcb instructions without inheriting Zca for testing purposes
55#[instruction]
56#[derive(Debug, Clone, Copy)]
57#[derive_const(PartialEq, Eq)]
58#[rustfmt::skip]
59#[doc(hidden)]
60pub enum Rv64ZcbOnlyInstruction<Reg> {
61    // Q00 loads / stores
62    /// C.LBU  rd' = zero_extend(mem8\[rs1' + uimm])  uimm ∈ {0,1,2,3}
63    CLbu { rd: Reg, rs1: Reg, uimm: u8 },
64    /// C.LH   rd' = sign_extend(mem16\[rs1' + uimm])  uimm ∈ {0,2}
65    CLh { rd: Reg, rs1: Reg, uimm: u8 },
66    /// C.LHU  rd' = zero_extend(mem16\[rs1' + uimm])  uimm ∈ {0,2}
67    CLhu { rd: Reg, rs1: Reg, uimm: u8 },
68    /// C.SB   mem8\[rs1' + uimm] = rs2'  uimm ∈ {0,1,2,3}
69    CSb { rs1: Reg, rs2: Reg, uimm: u8 },
70    /// C.SH   mem16\[rs1' + uimm] = rs2'  uimm ∈ {0,2}
71    CSh { rs1: Reg, rs2: Reg, uimm: u8 },
72
73    // Q01 unary bit-manipulation
74    /// C.ZEXT.B  rd' = rd' & 0xff
75    CZextB { rd: Reg },
76    /// C.SEXT.B  rd' = sext(rd'\[7:0])  (requires Zbb)
77    #[instruction(if = [Rv64ZbbInstruction])]
78    CSextB { rd: Reg },
79    /// C.ZEXT.H  rd' = rd' & 0xffff  (requires Zbb)
80    #[instruction(if = [Rv64ZbbInstruction])]
81    CZextH { rd: Reg },
82    /// C.SEXT.H  rd' = sext(rd'\[15:0])  (requires Zbb)
83    #[instruction(if = [Rv64ZbbInstruction])]
84    CSextH { rd: Reg },
85    /// C.ZEXT.W  rd' = rd' & 0xffff_ffff  (requires Zba)
86    #[instruction(if = [Rv64ZbaInstruction])]
87    CZextW { rd: Reg },
88    /// C.NOT  rd' = ~rd'
89    CNot { rd: Reg },
90
91    // Q01 binary
92    /// C.MUL  rd' = (rd' * rs2')\[XLEN-1:0]  (requires M or Zmmul)
93    #[instruction(
94        if = [Rv64MInstruction],
95        if = [Rv64ZmmulInstruction]
96    )]
97    CMul { rd: Reg, rs2: Reg },
98}
99
100#[instruction]
101const impl<Reg> Instruction for Rv64ZcbOnlyInstruction<Reg>
102where
103    Reg: [const] Register<Type = u64>,
104{
105    const ALIGNMENT: u8 = align_of::<u16>() as u8;
106
107    type Reg = Reg;
108
109    #[inline(always)]
110    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
111    fn try_decode(instruction: u32) -> Option<Self> {
112        /// Map a 3-bit "prime" register field to an absolute register number
113        #[inline(always)]
114        const fn prime_reg_bits(bits: u8) -> u8 {
115            bits + 8
116        }
117
118        let inst = instruction as u16;
119        let quadrant = inst & 0b11;
120        let funct3 = ((inst >> 13) & 0b111) as u8;
121
122        match quadrant {
123            // Q00 funct3=100: C.LBU / C.LHU / C.LH / C.SB / C.SH
124            0b00 if funct3 == 0b100 => {
125                let sub = ((inst >> 10) & 0b111) as u8;
126                let rs1_bits = prime_reg_bits(((inst >> 7) & 0b111) as u8);
127                let rd_rs2_bits = prime_reg_bits(((inst >> 2) & 0b111) as u8);
128
129                match sub {
130                    // C.LBU  uimm[1]=inst[5], uimm[0]=inst[6]
131                    0b000 => {
132                        let uimm = ((((inst >> 5) & 1) << 1) | ((inst >> 6) & 1)) as u8;
133                        let rs1 = Reg::from_bits(rs1_bits)?;
134                        let rd = Reg::from_bits(rd_rs2_bits)?;
135                        Some(Self::CLbu { rd, rs1, uimm })
136                    }
137                    // C.LHU (funct1=inst[6]=0) / C.LH (funct1=inst[6]=1)
138                    // uimm[1]=inst[5], uimm[0]=0 (halfword aligned)
139                    0b001 => {
140                        let funct1 = ((inst >> 6) & 1) as u8;
141                        let uimm = (((inst >> 5) & 1) as u8) << 1;
142                        let rs1 = Reg::from_bits(rs1_bits)?;
143                        let rd = Reg::from_bits(rd_rs2_bits)?;
144                        if funct1 == 0 {
145                            Some(Self::CLhu { rd, rs1, uimm })
146                        } else {
147                            Some(Self::CLh { rd, rs1, uimm })
148                        }
149                    }
150                    // C.SB  uimm[1]=inst[5], uimm[0]=inst[6]
151                    0b010 => {
152                        let uimm = ((((inst >> 5) & 1) << 1) | ((inst >> 6) & 1)) as u8;
153                        let rs1 = Reg::from_bits(rs1_bits)?;
154                        let rs2 = Reg::from_bits(rd_rs2_bits)?;
155                        Some(Self::CSb { rs1, rs2, uimm })
156                    }
157                    // C.SH  funct1=inst[6]=0, uimm[1]=inst[5]
158                    0b011 => {
159                        if ((inst >> 6) & 1) != 0 {
160                            None?;
161                        }
162                        let uimm = (((inst >> 5) & 1) as u8) << 1;
163                        let rs1 = Reg::from_bits(rs1_bits)?;
164                        let rs2 = Reg::from_bits(rd_rs2_bits)?;
165                        Some(Self::CSh { rs1, rs2, uimm })
166                    }
167                    _ => None,
168                }
169            }
170
171            // Q01 funct3=100, funct2[11:10]=11, bit12=1: unary ops and C.MUL
172            //
173            // Encoding layout (per ratified Zcb spec):
174            //   funct2b = inst[6:5]
175            //   0b11 => unary ops, sub-op = inst[4:2]
176            //   0b10 => C.MUL, rs2' = inst[4:2]
177            //   0b00, 0b01 => reserved
178            0b01 if funct3 == 0b100 => {
179                let funct2_11_10 = ((inst >> 10) & 0b11) as u8;
180                let bit12 = (inst >> 12) & 1;
181
182                if funct2_11_10 != 0b11 || bit12 == 0 {
183                    None?;
184                }
185
186                let rd_rs1_bits = prime_reg_bits(((inst >> 7) & 0b111) as u8);
187                let funct2b = ((inst >> 5) & 0b11) as u8;
188                let rs2_sub = ((inst >> 2) & 0b111) as u8;
189
190                match funct2b {
191                    // Unary ops: funct2b=0b11, sub-op in inst[4:2]
192                    0b11 => {
193                        let rd = Reg::from_bits(rd_rs1_bits)?;
194                        match rs2_sub {
195                            0b000 => Some(Self::CZextB { rd }),
196                            0b001 => Some(Self::CSextB { rd }),
197                            0b010 => Some(Self::CZextH { rd }),
198                            0b011 => Some(Self::CSextH { rd }),
199                            0b100 => Some(Self::CZextW { rd }),
200                            0b101 => Some(Self::CNot { rd }),
201                            // 110, 111 reserved
202                            _ => None,
203                        }
204                    }
205                    // C.MUL: funct2b=0b10, rs2' = inst[4:2]
206                    0b10 => {
207                        let rd = Reg::from_bits(rd_rs1_bits)?;
208                        let rs2 = Reg::from_bits(prime_reg_bits(rs2_sub))?;
209                        Some(Self::CMul { rd, rs2 })
210                    }
211                    // funct2b=0b00 and funct2b=0b01 are reserved in Zcb
212                    _ => None,
213                }
214            }
215
216            _ => None,
217        }
218    }
219
220    #[inline(always)]
221    fn size(&self) -> u8 {
222        size_of::<u16>() as u8
223    }
224}
225
226#[instruction]
227impl<Reg> fmt::Display for Rv64ZcbOnlyInstruction<Reg>
228where
229    Reg: fmt::Display + Copy,
230{
231    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
232        match self {
233            Self::CLbu { rd, rs1, uimm } => write!(f, "c.lbu {rd}, {uimm}({rs1})"),
234            Self::CLh { rd, rs1, uimm } => write!(f, "c.lh {rd}, {uimm}({rs1})"),
235            Self::CLhu { rd, rs1, uimm } => write!(f, "c.lhu {rd}, {uimm}({rs1})"),
236            Self::CSb { rs1, rs2, uimm } => write!(f, "c.sb {rs2}, {uimm}({rs1})"),
237            Self::CSh { rs1, rs2, uimm } => write!(f, "c.sh {rs2}, {uimm}({rs1})"),
238            Self::CZextB { rd } => write!(f, "c.zext.b {rd}"),
239            Self::CSextB { rd } => write!(f, "c.sext.b {rd}"),
240            Self::CZextH { rd } => write!(f, "c.zext.h {rd}"),
241            Self::CSextH { rd } => write!(f, "c.sext.h {rd}"),
242            Self::CZextW { rd } => write!(f, "c.zext.w {rd}"),
243            Self::CNot { rd } => write!(f, "c.not {rd}"),
244            Self::CMul { rd, rs2 } => write!(f, "c.mul {rd}, {rs2}"),
245        }
246    }
247}
ab_riscv_primitives/instructions/rv64/zce/zcb.rs

ab_riscv_primitives/instructions/rv64/zce/
zcb.rs
