ab_riscv_primitives/instructions/rv64/zce/
zcb.rs

1//! RV64 Zcb extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::instructions::rv64::c::zca::Rv64ZcaInstruction;
8use crate::instructions::utils::I24;
9use crate::registers::general_purpose::Register;
10use ab_riscv_macros::instruction;
11use core::fmt;
12
13/// RISC-V RV64 Zcb compressed instruction set.
14///
15/// All register operands are prime-field (x8–x15) registers.
16#[instruction(
17    inherit = [Rv64ZcaInstruction, Rv64ZcbOnlyInstruction],
18)]
19#[derive(Debug, Clone, Copy, PartialEq, Eq)]
20pub enum Rv64ZcbInstruction<Reg> {}
21
22#[instruction]
23impl<Reg> const Instruction for Rv64ZcbInstruction<Reg>
24where
25    Reg: [const] Register<Type = u64>,
26{
27    type Reg = Reg;
28
29    #[inline(always)]
30    fn try_decode(instruction: u32) -> Option<Self> {
31        None
32    }
33
34    #[inline(always)]
35    fn alignment() -> u8 {
36        align_of::<u16>() as u8
37    }
38
39    #[inline(always)]
40    fn size(&self) -> u8 {
41        size_of::<u16>() as u8
42    }
43}
44
45#[instruction]
46impl<Reg> fmt::Display for Rv64ZcbInstruction<Reg>
47where
48    Reg: fmt::Display + Copy,
49{
50    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
51        match self {}
52    }
53}
54
55/// Instruction that contains isolated Zcb instructions without inheriting Zca for testing purposes
56#[instruction]
57#[derive(Debug, Clone, Copy, PartialEq, Eq)]
58#[rustfmt::skip]
59#[doc(hidden)]
60pub enum Rv64ZcbOnlyInstruction<Reg> {
61    // Q00 loads / stores
62    /// C.LBU  rd' = zero_extend(mem8\[rs1' + uimm])  uimm ∈ {0,1,2,3}
63    CLbu { rd: Reg, rs1: Reg, uimm: u8 },
64    /// C.LH   rd' = sign_extend(mem16\[rs1' + uimm])  uimm ∈ {0,2}
65    CLh { rd: Reg, rs1: Reg, uimm: u8 },
66    /// C.LHU  rd' = zero_extend(mem16\[rs1' + uimm])  uimm ∈ {0,2}
67    CLhu { rd: Reg, rs1: Reg, uimm: u8 },
68    /// C.SB   mem8\[rs1' + uimm] = rs2'  uimm ∈ {0,1,2,3}
69    CSb { rs1: Reg, rs2: Reg, uimm: u8 },
70    /// C.SH   mem16\[rs1' + uimm] = rs2'  uimm ∈ {0,2}
71    CSh { rs1: Reg, rs2: Reg, uimm: u8 },
72
73    // Q01 unary bit-manipulation
74    /// C.ZEXT.B  rd' = rd' & 0xff
75    CZextB { rd: Reg },
76    /// C.SEXT.B  rd' = sext(rd'\[7:0])  (requires Zbb)
77    #[instruction(if = [Rv64ZbbInstruction])]
78    CSextB { rd: Reg },
79    /// C.ZEXT.H  rd' = rd' & 0xffff  (requires Zbb)
80    #[instruction(if = [Rv64ZbbInstruction])]
81    CZextH { rd: Reg },
82    /// C.SEXT.H  rd' = sext(rd'\[15:0])  (requires Zbb)
83    #[instruction(if = [Rv64ZbbInstruction])]
84    CSextH { rd: Reg },
85    /// C.ZEXT.W  rd' = rd' & 0xffff_ffff  (requires Zba)
86    #[instruction(if = [Rv64ZbaInstruction])]
87    CZextW { rd: Reg },
88    /// C.NOT  rd' = ~rd'
89    CNot { rd: Reg },
90
91    // Q01 binary
92    /// C.MUL  rd' = (rd' * rs2')\[XLEN-1:0]  (requires M or Zmmul)
93    #[instruction(
94        if = [Rv64MInstruction],
95        if = [Rv64ZmmulInstruction]
96    )]
97    CMul { rd: Reg, rs2: Reg },
98}
99
100#[instruction]
101impl<Reg> const Instruction for Rv64ZcbOnlyInstruction<Reg>
102where
103    Reg: [const] Register<Type = u64>,
104{
105    type Reg = Reg;
106
107    #[inline(always)]
108    fn try_decode(instruction: u32) -> Option<Self> {
109        /// Map a 3-bit "prime" register field to an absolute register number
110        #[inline(always)]
111        const fn prime_reg_bits(bits: u8) -> u8 {
112            bits + 8
113        }
114
115        let inst = instruction as u16;
116        let quadrant = inst & 0b11;
117        let funct3 = ((inst >> 13) & 0b111) as u8;
118
119        match quadrant {
120            // Q00 funct3=100: C.LBU / C.LHU / C.LH / C.SB / C.SH
121            0b00 if funct3 == 0b100 => {
122                let sub = ((inst >> 10) & 0b111) as u8;
123                let rs1_bits = prime_reg_bits(((inst >> 7) & 0b111) as u8);
124                let rd_rs2_bits = prime_reg_bits(((inst >> 2) & 0b111) as u8);
125
126                match sub {
127                    // C.LBU  uimm[1]=inst[5], uimm[0]=inst[6]
128                    0b000 => {
129                        let uimm = ((((inst >> 5) & 1) << 1) | ((inst >> 6) & 1)) as u8;
130                        let rs1 = Reg::from_bits(rs1_bits)?;
131                        let rd = Reg::from_bits(rd_rs2_bits)?;
132                        Some(Self::CLbu { rd, rs1, uimm })
133                    }
134                    // C.LHU (funct1=inst[6]=0) / C.LH (funct1=inst[6]=1)
135                    // uimm[1]=inst[5], uimm[0]=0 (halfword aligned)
136                    0b001 => {
137                        let funct1 = ((inst >> 6) & 1) as u8;
138                        let uimm = (((inst >> 5) & 1) as u8) << 1;
139                        let rs1 = Reg::from_bits(rs1_bits)?;
140                        let rd = Reg::from_bits(rd_rs2_bits)?;
141                        if funct1 == 0 {
142                            Some(Self::CLhu { rd, rs1, uimm })
143                        } else {
144                            Some(Self::CLh { rd, rs1, uimm })
145                        }
146                    }
147                    // C.SB  uimm[1]=inst[5], uimm[0]=inst[6]
148                    0b010 => {
149                        let uimm = ((((inst >> 5) & 1) << 1) | ((inst >> 6) & 1)) as u8;
150                        let rs1 = Reg::from_bits(rs1_bits)?;
151                        let rs2 = Reg::from_bits(rd_rs2_bits)?;
152                        Some(Self::CSb { rs1, rs2, uimm })
153                    }
154                    // C.SH  funct1=inst[6]=0, uimm[1]=inst[5]
155                    0b011 => {
156                        if ((inst >> 6) & 1) != 0 {
157                            None?;
158                        }
159                        let uimm = (((inst >> 5) & 1) as u8) << 1;
160                        let rs1 = Reg::from_bits(rs1_bits)?;
161                        let rs2 = Reg::from_bits(rd_rs2_bits)?;
162                        Some(Self::CSh { rs1, rs2, uimm })
163                    }
164                    _ => None,
165                }
166            }
167
168            // Q01 funct3=100, funct2[11:10]=11, bit12=1: unary ops and C.MUL
169            //
170            // Encoding layout (per ratified Zcb spec):
171            //   funct2b = inst[6:5]
172            //   0b11 => unary ops, sub-op = inst[4:2]
173            //   0b10 => C.MUL, rs2' = inst[4:2]
174            //   0b00, 0b01 => reserved
175            0b01 if funct3 == 0b100 => {
176                let funct2_11_10 = ((inst >> 10) & 0b11) as u8;
177                let bit12 = (inst >> 12) & 1;
178
179                if funct2_11_10 != 0b11 || bit12 == 0 {
180                    None?;
181                }
182
183                let rd_rs1_bits = prime_reg_bits(((inst >> 7) & 0b111) as u8);
184                let funct2b = ((inst >> 5) & 0b11) as u8;
185                let rs2_sub = ((inst >> 2) & 0b111) as u8;
186
187                match funct2b {
188                    // Unary ops: funct2b=0b11, sub-op in inst[4:2]
189                    0b11 => {
190                        let rd = Reg::from_bits(rd_rs1_bits)?;
191                        match rs2_sub {
192                            0b000 => Some(Self::CZextB { rd }),
193                            0b001 => Some(Self::CSextB { rd }),
194                            0b010 => Some(Self::CZextH { rd }),
195                            0b011 => Some(Self::CSextH { rd }),
196                            0b100 => Some(Self::CZextW { rd }),
197                            0b101 => Some(Self::CNot { rd }),
198                            // 110, 111 reserved
199                            _ => None,
200                        }
201                    }
202                    // C.MUL: funct2b=0b10, rs2' = inst[4:2]
203                    0b10 => {
204                        let rd = Reg::from_bits(rd_rs1_bits)?;
205                        let rs2 = Reg::from_bits(prime_reg_bits(rs2_sub))?;
206                        Some(Self::CMul { rd, rs2 })
207                    }
208                    // funct2b=0b00 and funct2b=0b01 are reserved in Zcb
209                    _ => None,
210                }
211            }
212
213            _ => None,
214        }
215    }
216
217    #[inline(always)]
218    fn alignment() -> u8 {
219        align_of::<u16>() as u8
220    }
221
222    #[inline(always)]
223    fn size(&self) -> u8 {
224        size_of::<u16>() as u8
225    }
226}
227
228#[instruction]
229impl<Reg> fmt::Display for Rv64ZcbOnlyInstruction<Reg>
230where
231    Reg: fmt::Display + Copy,
232{
233    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
234        match self {
235            Self::CLbu { rd, rs1, uimm } => write!(f, "c.lbu {rd}, {uimm}({rs1})"),
236            Self::CLh { rd, rs1, uimm } => write!(f, "c.lh {rd}, {uimm}({rs1})"),
237            Self::CLhu { rd, rs1, uimm } => write!(f, "c.lhu {rd}, {uimm}({rs1})"),
238            Self::CSb { rs1, rs2, uimm } => write!(f, "c.sb {rs2}, {uimm}({rs1})"),
239            Self::CSh { rs1, rs2, uimm } => write!(f, "c.sh {rs2}, {uimm}({rs1})"),
240            Self::CZextB { rd } => write!(f, "c.zext.b {rd}"),
241            Self::CSextB { rd } => write!(f, "c.sext.b {rd}"),
242            Self::CZextH { rd } => write!(f, "c.zext.h {rd}"),
243            Self::CSextH { rd } => write!(f, "c.sext.h {rd}"),
244            Self::CZextW { rd } => write!(f, "c.zext.w {rd}"),
245            Self::CNot { rd } => write!(f, "c.not {rd}"),
246            Self::CMul { rd, rs2 } => write!(f, "c.mul {rd}, {rs2}"),
247        }
248    }
249}
ab_riscv_primitives/instructions/rv64/zce/zcb.rs

ab_riscv_primitives/instructions/rv64/zce/
zcb.rs
