ab_riscv_primitives/instructions/rv64/
zalasr.rs

1//! RV64 Zalasr extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11/// RISC-V RV64 Zalasr instruction (Load-Acquire/Store-Release).
12///
13/// Load-acquire instructions always carry an acquire annotation (not stored as a field since it
14/// is always `true`), plus an optional release annotation stored in `rl`. Store-release
15/// instructions always carry a release annotation (not stored as a field since it is always
16/// `true`), plus an optional acquire annotation stored in `aq`.
17#[instruction]
18#[derive(Debug, Clone, Copy)]
19#[derive_const(PartialEq, Eq)]
20pub enum Rv64ZalasrInstruction<Reg> {
21    /// Load-acquire byte
22    LbAq { rd: Reg, rs1: Reg, rl: bool },
23    /// Load-acquire halfword
24    LhAq { rd: Reg, rs1: Reg, rl: bool },
25    /// Load-acquire word
26    LwAq { rd: Reg, rs1: Reg, rl: bool },
27    /// Load-acquire doubleword
28    LdAq { rd: Reg, rs1: Reg, rl: bool },
29    /// Store-release byte
30    SbRl { rs1: Reg, rs2: Reg, aq: bool },
31    /// Store-release halfword
32    ShRl { rs1: Reg, rs2: Reg, aq: bool },
33    /// Store-release word
34    SwRl { rs1: Reg, rs2: Reg, aq: bool },
35    /// Store-release doubleword
36    SdRl { rs1: Reg, rs2: Reg, aq: bool },
37}
38
39#[instruction]
40const impl<Reg> Instruction for Rv64ZalasrInstruction<Reg>
41where
42    Reg: [const] Register<Type = u64>,
43{
44    const ALIGNMENT: u8 = align_of::<u32>() as u8;
45
46    type Reg = Reg;
47
48    #[inline(always)]
49    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
50    fn try_decode(instruction: u32) -> Option<Self> {
51        let opcode = (instruction & 0b111_1111) as u8;
52        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
53        let funct3 = ((instruction >> 12) & 0b111) as u8;
54        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
55        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
56        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
57        let funct5 = funct7 >> 2;
58        let aq = (funct7 & 0b10) != 0;
59        let rl = (funct7 & 0b01) != 0;
60
61        match (opcode, funct5) {
62            // Load-acquire, `aq` bit is mandatory and `rs2` must be zero
63            (0b010_1111, 0b00110) => match (funct3, rs2_bits, aq) {
64                (0b000, 0, true) => {
65                    let rd = Reg::from_bits(rd_bits)?;
66                    let rs1 = Reg::from_bits(rs1_bits)?;
67                    Some(Self::LbAq { rd, rs1, rl })
68                }
69                (0b001, 0, true) => {
70                    let rd = Reg::from_bits(rd_bits)?;
71                    let rs1 = Reg::from_bits(rs1_bits)?;
72                    Some(Self::LhAq { rd, rs1, rl })
73                }
74                (0b010, 0, true) => {
75                    let rd = Reg::from_bits(rd_bits)?;
76                    let rs1 = Reg::from_bits(rs1_bits)?;
77                    Some(Self::LwAq { rd, rs1, rl })
78                }
79                (0b011, 0, true) => {
80                    let rd = Reg::from_bits(rd_bits)?;
81                    let rs1 = Reg::from_bits(rs1_bits)?;
82                    Some(Self::LdAq { rd, rs1, rl })
83                }
84                _ => None,
85            },
86            // Store-release, `rl` bit is mandatory and `rd` must be zero
87            (0b010_1111, 0b00111) => match (funct3, rd_bits, rl) {
88                (0b000, 0, true) => {
89                    let rs1 = Reg::from_bits(rs1_bits)?;
90                    let rs2 = Reg::from_bits(rs2_bits)?;
91                    Some(Self::SbRl { rs1, rs2, aq })
92                }
93                (0b001, 0, true) => {
94                    let rs1 = Reg::from_bits(rs1_bits)?;
95                    let rs2 = Reg::from_bits(rs2_bits)?;
96                    Some(Self::ShRl { rs1, rs2, aq })
97                }
98                (0b010, 0, true) => {
99                    let rs1 = Reg::from_bits(rs1_bits)?;
100                    let rs2 = Reg::from_bits(rs2_bits)?;
101                    Some(Self::SwRl { rs1, rs2, aq })
102                }
103                (0b011, 0, true) => {
104                    let rs1 = Reg::from_bits(rs1_bits)?;
105                    let rs2 = Reg::from_bits(rs2_bits)?;
106                    Some(Self::SdRl { rs1, rs2, aq })
107                }
108                _ => None,
109            },
110            _ => None,
111        }
112    }
113
114    #[inline(always)]
115    fn size(&self) -> u8 {
116        size_of::<u32>() as u8
117    }
118}
119
120/// Format optional `rl` suffix for load-acquire display
121#[inline(always)]
122fn rl_suffix(rl: &bool) -> &'static str {
123    if *rl { ".aqrl" } else { ".aq" }
124}
125
126/// Format optional `aq` suffix for store-release display
127#[inline(always)]
128fn aq_suffix(aq: &bool) -> &'static str {
129    if *aq { ".aqrl" } else { ".rl" }
130}
131
132#[instruction]
133impl<Reg> fmt::Display for Rv64ZalasrInstruction<Reg>
134where
135    Reg: fmt::Display,
136{
137    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
138        match self {
139            Self::LbAq { rd, rs1, rl } => write!(f, "lb{} {rd}, ({rs1})", rl_suffix(rl)),
140            Self::LhAq { rd, rs1, rl } => write!(f, "lh{} {rd}, ({rs1})", rl_suffix(rl)),
141            Self::LwAq { rd, rs1, rl } => write!(f, "lw{} {rd}, ({rs1})", rl_suffix(rl)),
142            Self::LdAq { rd, rs1, rl } => write!(f, "ld{} {rd}, ({rs1})", rl_suffix(rl)),
143            Self::SbRl { rs1, rs2, aq } => write!(f, "sb{} {rs2}, ({rs1})", aq_suffix(aq)),
144            Self::ShRl { rs1, rs2, aq } => write!(f, "sh{} {rs2}, ({rs1})", aq_suffix(aq)),
145            Self::SwRl { rs1, rs2, aq } => write!(f, "sw{} {rs2}, ({rs1})", aq_suffix(aq)),
146            Self::SdRl { rs1, rs2, aq } => write!(f, "sd{} {rs2}, ({rs1})", aq_suffix(aq)),
147        }
148    }
149}
ab_riscv_primitives/instructions/rv64/zalasr.rs

ab_riscv_primitives/instructions/rv64/
zalasr.rs
