ab_riscv_primitives/instructions/rv64/
zalasr.rs

1//! RV64 Zalasr extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::hart::HartConfig;
7use crate::instructions::{ImplementedExtension, Instruction, IsaExtension};
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12/// RISC-V RV64 Zalasr instruction (Load-Acquire/Store-Release).
13///
14/// Load-acquire instructions always carry an acquire annotation (not stored as a field since it
15/// is always `true`), plus an optional release annotation stored in `rl`. Store-release
16/// instructions always carry a release annotation (not stored as a field since it is always
17/// `true`), plus an optional acquire annotation stored in `aq`.
18#[instruction]
19#[derive(Debug, Clone, Copy)]
20#[derive_const(PartialEq, Eq)]
21#[rustfmt::skip]
22pub enum Rv64ZalasrInstruction<Hart>
23where
24    Hart: HartConfig,
25{
26    /// Load-acquire byte
27    LbAq { rd: Hart::Reg, rs1: Hart::Reg, rl: bool },
28    /// Load-acquire halfword
29    LhAq { rd: Hart::Reg, rs1: Hart::Reg, rl: bool },
30    /// Load-acquire word
31    LwAq { rd: Hart::Reg, rs1: Hart::Reg, rl: bool },
32    /// Load-acquire doubleword
33    LdAq { rd: Hart::Reg, rs1: Hart::Reg, rl: bool },
34    /// Store-release byte
35    SbRl { rs1: Hart::Reg, rs2: Hart::Reg, aq: bool },
36    /// Store-release halfword
37    ShRl { rs1: Hart::Reg, rs2: Hart::Reg, aq: bool },
38    /// Store-release word
39    SwRl { rs1: Hart::Reg, rs2: Hart::Reg, aq: bool },
40    /// Store-release doubleword
41    SdRl { rs1: Hart::Reg, rs2: Hart::Reg, aq: bool },
42}
43
44#[instruction]
45const impl<Reg, Hart> Instruction for Rv64ZalasrInstruction<Hart>
46where
47    Reg: [const] Register<Type = u64>,
48    Hart: [const] HartConfig<Reg = Reg>,
49{
50    const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = &[IsaExtension::new("zalasr", 1, 0)];
51
52    const ALIGNMENT: u8 = align_of::<u32>() as u8;
53
54    type Hart = Hart;
55
56    #[inline(always)]
57    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
58    fn try_decode(instruction: u32) -> Option<Self> {
59        let opcode = (instruction & 0b111_1111) as u8;
60        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
61        let funct3 = ((instruction >> 12) & 0b111) as u8;
62        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
63        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
64        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
65        let funct5 = funct7 >> 2;
66        let aq = (funct7 & 0b10) != 0;
67        let rl = (funct7 & 0b01) != 0;
68
69        match (opcode, funct5) {
70            // Load-acquire, `aq` bit is mandatory and `rs2` must be zero
71            (0b010_1111, 0b00110) => match (funct3, rs2_bits, aq) {
72                (0b000, 0, true) => {
73                    let rd = Reg::from_bits(rd_bits)?;
74                    let rs1 = Reg::from_bits(rs1_bits)?;
75                    Some(Self::LbAq { rd, rs1, rl })
76                }
77                (0b001, 0, true) => {
78                    let rd = Reg::from_bits(rd_bits)?;
79                    let rs1 = Reg::from_bits(rs1_bits)?;
80                    Some(Self::LhAq { rd, rs1, rl })
81                }
82                (0b010, 0, true) => {
83                    let rd = Reg::from_bits(rd_bits)?;
84                    let rs1 = Reg::from_bits(rs1_bits)?;
85                    Some(Self::LwAq { rd, rs1, rl })
86                }
87                (0b011, 0, true) => {
88                    let rd = Reg::from_bits(rd_bits)?;
89                    let rs1 = Reg::from_bits(rs1_bits)?;
90                    Some(Self::LdAq { rd, rs1, rl })
91                }
92                _ => None,
93            },
94            // Store-release, `rl` bit is mandatory and `rd` must be zero
95            (0b010_1111, 0b00111) => match (funct3, rd_bits, rl) {
96                (0b000, 0, true) => {
97                    let rs1 = Reg::from_bits(rs1_bits)?;
98                    let rs2 = Reg::from_bits(rs2_bits)?;
99                    Some(Self::SbRl { rs1, rs2, aq })
100                }
101                (0b001, 0, true) => {
102                    let rs1 = Reg::from_bits(rs1_bits)?;
103                    let rs2 = Reg::from_bits(rs2_bits)?;
104                    Some(Self::ShRl { rs1, rs2, aq })
105                }
106                (0b010, 0, true) => {
107                    let rs1 = Reg::from_bits(rs1_bits)?;
108                    let rs2 = Reg::from_bits(rs2_bits)?;
109                    Some(Self::SwRl { rs1, rs2, aq })
110                }
111                (0b011, 0, true) => {
112                    let rs1 = Reg::from_bits(rs1_bits)?;
113                    let rs2 = Reg::from_bits(rs2_bits)?;
114                    Some(Self::SdRl { rs1, rs2, aq })
115                }
116                _ => None,
117            },
118            _ => None,
119        }
120    }
121
122    #[inline(always)]
123    fn size(&self) -> u8 {
124        size_of::<u32>() as u8
125    }
126}
127
128/// Format optional `rl` suffix for load-acquire display
129#[inline(always)]
130fn rl_suffix(rl: &bool) -> &'static str {
131    if *rl { ".aqrl" } else { ".aq" }
132}
133
134/// Format optional `aq` suffix for store-release display
135#[inline(always)]
136fn aq_suffix(aq: &bool) -> &'static str {
137    if *aq { ".aqrl" } else { ".rl" }
138}
139
140#[instruction]
141impl<Reg, Hart> fmt::Display for Rv64ZalasrInstruction<Hart>
142where
143    Reg: fmt::Display,
144    Hart: HartConfig<Reg = Reg>,
145{
146    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
147        match self {
148            Self::LbAq { rd, rs1, rl } => write!(f, "lb{} {rd}, ({rs1})", rl_suffix(rl)),
149            Self::LhAq { rd, rs1, rl } => write!(f, "lh{} {rd}, ({rs1})", rl_suffix(rl)),
150            Self::LwAq { rd, rs1, rl } => write!(f, "lw{} {rd}, ({rs1})", rl_suffix(rl)),
151            Self::LdAq { rd, rs1, rl } => write!(f, "ld{} {rd}, ({rs1})", rl_suffix(rl)),
152            Self::SbRl { rs1, rs2, aq } => write!(f, "sb{} {rs2}, ({rs1})", aq_suffix(aq)),
153            Self::ShRl { rs1, rs2, aq } => write!(f, "sh{} {rs2}, ({rs1})", aq_suffix(aq)),
154            Self::SwRl { rs1, rs2, aq } => write!(f, "sw{} {rs2}, ({rs1})", aq_suffix(aq)),
155            Self::SdRl { rs1, rs2, aq } => write!(f, "sd{} {rs2}, ({rs1})", aq_suffix(aq)),
156        }
157    }
158}
ab_riscv_primitives/instructions/rv64/zalasr.rs

ab_riscv_primitives/instructions/rv64/
zalasr.rs
