ab_riscv_primitives/instructions/rv64/
zalasr.rs

1//! RV64 Zalasr extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11/// RISC-V RV64 Zalasr instruction (Load-Acquire/Store-Release).
12///
13/// Load-acquire instructions always carry an acquire annotation (not stored as a field since it
14/// is always `true`), plus an optional release annotation stored in `rl`. Store-release
15/// instructions always carry a release annotation (not stored as a field since it is always
16/// `true`), plus an optional acquire annotation stored in `aq`.
17#[instruction]
18#[derive(Debug, Clone, Copy)]
19#[derive_const(PartialEq, Eq)]
20pub enum Rv64ZalasrInstruction<Reg> {
21    /// Load-acquire byte
22    LbAq { rd: Reg, rs1: Reg, rl: bool },
23    /// Load-acquire halfword
24    LhAq { rd: Reg, rs1: Reg, rl: bool },
25    /// Load-acquire word
26    LwAq { rd: Reg, rs1: Reg, rl: bool },
27    /// Load-acquire doubleword
28    LdAq { rd: Reg, rs1: Reg, rl: bool },
29    /// Store-release byte
30    SbRl { rs1: Reg, rs2: Reg, aq: bool },
31    /// Store-release halfword
32    ShRl { rs1: Reg, rs2: Reg, aq: bool },
33    /// Store-release word
34    SwRl { rs1: Reg, rs2: Reg, aq: bool },
35    /// Store-release doubleword
36    SdRl { rs1: Reg, rs2: Reg, aq: bool },
37}
38
39#[instruction]
40const impl<Reg> Instruction for Rv64ZalasrInstruction<Reg>
41where
42    Reg: [const] Register<Type = u64>,
43{
44    type Reg = Reg;
45
46    #[inline(always)]
47    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
48    fn try_decode(instruction: u32) -> Option<Self> {
49        let opcode = (instruction & 0b111_1111) as u8;
50        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
51        let funct3 = ((instruction >> 12) & 0b111) as u8;
52        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
53        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
54        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
55        let funct5 = funct7 >> 2;
56        let aq = (funct7 & 0b10) != 0;
57        let rl = (funct7 & 0b01) != 0;
58
59        match (opcode, funct5) {
60            // Load-acquire, `aq` bit is mandatory and `rs2` must be zero
61            (0b010_1111, 0b00110) => match (funct3, rs2_bits, aq) {
62                (0b000, 0, true) => {
63                    let rd = Reg::from_bits(rd_bits)?;
64                    let rs1 = Reg::from_bits(rs1_bits)?;
65                    Some(Self::LbAq { rd, rs1, rl })
66                }
67                (0b001, 0, true) => {
68                    let rd = Reg::from_bits(rd_bits)?;
69                    let rs1 = Reg::from_bits(rs1_bits)?;
70                    Some(Self::LhAq { rd, rs1, rl })
71                }
72                (0b010, 0, true) => {
73                    let rd = Reg::from_bits(rd_bits)?;
74                    let rs1 = Reg::from_bits(rs1_bits)?;
75                    Some(Self::LwAq { rd, rs1, rl })
76                }
77                (0b011, 0, true) => {
78                    let rd = Reg::from_bits(rd_bits)?;
79                    let rs1 = Reg::from_bits(rs1_bits)?;
80                    Some(Self::LdAq { rd, rs1, rl })
81                }
82                _ => None,
83            },
84            // Store-release, `rl` bit is mandatory and `rd` must be zero
85            (0b010_1111, 0b00111) => match (funct3, rd_bits, rl) {
86                (0b000, 0, true) => {
87                    let rs1 = Reg::from_bits(rs1_bits)?;
88                    let rs2 = Reg::from_bits(rs2_bits)?;
89                    Some(Self::SbRl { rs1, rs2, aq })
90                }
91                (0b001, 0, true) => {
92                    let rs1 = Reg::from_bits(rs1_bits)?;
93                    let rs2 = Reg::from_bits(rs2_bits)?;
94                    Some(Self::ShRl { rs1, rs2, aq })
95                }
96                (0b010, 0, true) => {
97                    let rs1 = Reg::from_bits(rs1_bits)?;
98                    let rs2 = Reg::from_bits(rs2_bits)?;
99                    Some(Self::SwRl { rs1, rs2, aq })
100                }
101                (0b011, 0, true) => {
102                    let rs1 = Reg::from_bits(rs1_bits)?;
103                    let rs2 = Reg::from_bits(rs2_bits)?;
104                    Some(Self::SdRl { rs1, rs2, aq })
105                }
106                _ => None,
107            },
108            _ => None,
109        }
110    }
111
112    #[inline(always)]
113    fn alignment() -> u8 {
114        align_of::<u32>() as u8
115    }
116
117    #[inline(always)]
118    fn size(&self) -> u8 {
119        size_of::<u32>() as u8
120    }
121}
122
123/// Format optional `rl` suffix for load-acquire display
124#[inline(always)]
125fn rl_suffix(rl: &bool) -> &'static str {
126    if *rl { ".aqrl" } else { ".aq" }
127}
128
129/// Format optional `aq` suffix for store-release display
130#[inline(always)]
131fn aq_suffix(aq: &bool) -> &'static str {
132    if *aq { ".aqrl" } else { ".rl" }
133}
134
135#[instruction]
136impl<Reg> fmt::Display for Rv64ZalasrInstruction<Reg>
137where
138    Reg: fmt::Display,
139{
140    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
141        match self {
142            Self::LbAq { rd, rs1, rl } => write!(f, "lb{} {rd}, ({rs1})", rl_suffix(rl)),
143            Self::LhAq { rd, rs1, rl } => write!(f, "lh{} {rd}, ({rs1})", rl_suffix(rl)),
144            Self::LwAq { rd, rs1, rl } => write!(f, "lw{} {rd}, ({rs1})", rl_suffix(rl)),
145            Self::LdAq { rd, rs1, rl } => write!(f, "ld{} {rd}, ({rs1})", rl_suffix(rl)),
146            Self::SbRl { rs1, rs2, aq } => write!(f, "sb{} {rs2}, ({rs1})", aq_suffix(aq)),
147            Self::ShRl { rs1, rs2, aq } => write!(f, "sh{} {rs2}, ({rs1})", aq_suffix(aq)),
148            Self::SwRl { rs1, rs2, aq } => write!(f, "sw{} {rs2}, ({rs1})", aq_suffix(aq)),
149            Self::SdRl { rs1, rs2, aq } => write!(f, "sd{} {rs2}, ({rs1})", aq_suffix(aq)),
150        }
151    }
152}
ab_riscv_primitives/instructions/rv64/zalasr.rs

ab_riscv_primitives/instructions/rv64/
zalasr.rs
