ab_riscv_primitives/instructions/rv64/
zacas.rs

1//! RV64 Zacas extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::hart::HartConfig;
7use crate::instructions::rv64::a::zaamo::Rv64ZaamoInstruction;
8use crate::instructions::{ImplementedExtension, Instruction, IsaExtension};
9use crate::registers::general_purpose::Register;
10use ab_riscv_macros::instruction;
11use core::fmt;
12
13/// RISC-V RV64 Zacas instruction (Atomic Compare-and-Swap)
14#[instruction(inherit = [Rv64ZaamoInstruction])]
15#[derive(Debug, Clone, Copy)]
16#[derive_const(PartialEq, Eq)]
17#[rustfmt::skip]
18pub enum Rv64ZacasInstruction<Hart>
19where
20    Hart: HartConfig,
21{
22    /// Compare-and-swap word
23    AmocasW { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg, aq: bool, rl: bool },
24    /// Compare-and-swap doubleword
25    AmocasD { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg, aq: bool, rl: bool },
26    // TODO: Register pairs are not enforced by types. Decoding only produces even `rd` and `rs2`
27    //  with `rd_hi` and `rs2_hi` being the registers right after them, and execution relies on that
28    //  instead of checking it again, like with other invariants checked by the decoder, so manually
29    //  constructed instructions can use arbitrary registers (not a memory safety issue). A type for
30    //  register pairs isn't an option yet: every instruction stores `rs1` and `rs2` with the same
31    //  type at the same position, so that reading operands compiles to reads at fixed offsets.
32    //  Revisit once `rs1` and `rs2` are no longer added to every instruction unconditionally, which
33    //  requires https://github.com/rust-lang/rfcs/pull/4001.
34    /// Compare-and-swap quadword, using register pairs `(rd, rd_hi)` and `(rs2, rs2_hi)` since
35    /// RV64 registers are only 64 bits wide.
36    AmocasQ { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg, rd_hi: Hart::Reg, rs2_hi: Hart::Reg, aq: bool, rl: bool },
37}
38
39#[instruction]
40const impl<Reg, Hart> Instruction for Rv64ZacasInstruction<Hart>
41where
42    Reg: [const] Register<Type = u64>,
43    Hart: [const] HartConfig<Reg = Reg>,
44{
45    const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = &[IsaExtension::new("zacas", 1, 0)];
46
47    const ALIGNMENT: u8 = align_of::<u32>() as u8;
48
49    type Hart = Hart;
50
51    #[inline(always)]
52    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
53    fn try_decode(instruction: u32) -> Option<Self> {
54        let opcode = (instruction & 0b111_1111) as u8;
55        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
56        let funct3 = ((instruction >> 12) & 0b111) as u8;
57        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
58        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
59        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
60
61        match (opcode, funct3, funct7 >> 2) {
62            // AMOCAS.W
63            (0b010_1111, 0b010, 0b00101) => {
64                let rd = Reg::from_bits(rd_bits)?;
65                let rs1 = Reg::from_bits(rs1_bits)?;
66                let rs2 = Reg::from_bits(rs2_bits)?;
67                let aq = (funct7 & 0b10) != 0;
68                let rl = (funct7 & 0b01) != 0;
69
70                Some(Self::AmocasW {
71                    rd,
72                    rs1,
73                    rs2,
74                    aq,
75                    rl,
76                })
77            }
78            // AMOCAS.D
79            (0b010_1111, 0b011, 0b00101) => {
80                let rd = Reg::from_bits(rd_bits)?;
81                let rs1 = Reg::from_bits(rs1_bits)?;
82                let rs2 = Reg::from_bits(rs2_bits)?;
83                let aq = (funct7 & 0b10) != 0;
84                let rl = (funct7 & 0b01) != 0;
85
86                Some(Self::AmocasD {
87                    rd,
88                    rs1,
89                    rs2,
90                    aq,
91                    rl,
92                })
93            }
94            // AMOCAS.Q, register-pair mode (RV64)
95            (0b010_1111, 0b100, 0b00101) => {
96                match (rd_bits & 1, rs2_bits & 1) {
97                    // Both halves of the register pairs must be even numbered, otherwise the
98                    // encoding is reserved
99                    (0, 0) => {
100                        let rs1 = Reg::from_bits(rs1_bits)?;
101                        let rd = Reg::from_bits(rd_bits)?;
102                        let rd_hi = Reg::from_bits(rd_bits + 1)?;
103                        let rs2 = Reg::from_bits(rs2_bits)?;
104                        let rs2_hi = Reg::from_bits(rs2_bits + 1)?;
105                        let aq = (funct7 & 0b10) != 0;
106                        let rl = (funct7 & 0b01) != 0;
107
108                        Some(Self::AmocasQ {
109                            rd,
110                            rs1,
111                            rs2,
112                            rd_hi,
113                            rs2_hi,
114                            aq,
115                            rl,
116                        })
117                    }
118                    _ => None,
119                }
120            }
121            _ => None,
122        }
123    }
124
125    #[inline(always)]
126    fn size(&self) -> u8 {
127        size_of::<u32>() as u8
128    }
129}
130
131/// Format `aq`/`rl` suffix for display
132#[inline(always)]
133fn aq_rl_suffix(aq: &bool, rl: &bool) -> &'static str {
134    match (*aq, *rl) {
135        (false, false) => "",
136        (true, false) => ".aq",
137        (false, true) => ".rl",
138        (true, true) => ".aqrl",
139    }
140}
141
142#[instruction]
143impl<Reg, Hart> fmt::Display for Rv64ZacasInstruction<Hart>
144where
145    Reg: fmt::Display + Copy,
146    Hart: HartConfig<Reg = Reg>,
147{
148    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
149        #[rustfmt::skip]
150        match self {
151            Self::AmocasW { rd, rs1, rs2, aq, rl } => write!(f, "amocas.w{} {rd}, {rs2}, ({rs1})", aq_rl_suffix(aq, rl)),
152            Self::AmocasD { rd, rs1, rs2, aq, rl } => write!(f, "amocas.d{} {rd}, {rs2}, ({rs1})", aq_rl_suffix(aq, rl)),
153            Self::AmocasQ { rd, rs1, rs2, rd_hi, rs2_hi, aq, rl } => write!(f, "amocas.q{} {rd}, {rd_hi}, {rs2}, {rs2_hi}, ({rs1})", aq_rl_suffix(aq, rl)),
154        }
155    }
156}
ab_riscv_primitives/instructions/rv64/zacas.rs

ab_riscv_primitives/instructions/rv64/
zacas.rs
