ab_riscv_primitives/instructions/rv64/
zacas.rs

1//! RV64 Zacas extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::instructions::rv64::a::zaamo::Rv64ZaamoInstruction;
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12/// RISC-V RV64 Zacas instruction (Atomic Compare-and-Swap)
13#[instruction(inherit = [Rv64ZaamoInstruction])]
14#[derive(Debug, Clone, Copy)]
15#[derive_const(PartialEq, Eq)]
16#[rustfmt::skip]
17pub enum Rv64ZacasInstruction<Reg> {
18    /// Compare-and-swap word
19    AmocasW { rd: Reg, rs1: Reg, rs2: Reg, aq: bool, rl: bool },
20    /// Compare-and-swap doubleword
21    AmocasD { rd: Reg, rs1: Reg, rs2: Reg, aq: bool, rl: bool },
22    /// Compare-and-swap quadword, using register pairs `(rd, rd_hi)` and `(rs2, rs2_hi)` since
23    /// RV64 registers are only 64 bits wide.
24    AmocasQ { rd: Reg, rs1: Reg, rs2: Reg, rd_hi: Reg, rs2_hi: Reg, aq: bool, rl: bool },
25}
26
27#[instruction]
28const impl<Reg> Instruction for Rv64ZacasInstruction<Reg>
29where
30    Reg: [const] Register<Type = u64>,
31{
32    type Reg = Reg;
33
34    #[inline(always)]
35    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
36    fn try_decode(instruction: u32) -> Option<Self> {
37        let opcode = (instruction & 0b111_1111) as u8;
38        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
39        let funct3 = ((instruction >> 12) & 0b111) as u8;
40        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
41        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
42        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
43
44        match (opcode, funct3, funct7 >> 2) {
45            // AMOCAS.W
46            (0b010_1111, 0b010, 0b00101) => {
47                let rd = Reg::from_bits(rd_bits)?;
48                let rs1 = Reg::from_bits(rs1_bits)?;
49                let rs2 = Reg::from_bits(rs2_bits)?;
50                let aq = (funct7 & 0b10) != 0;
51                let rl = (funct7 & 0b01) != 0;
52
53                Some(Self::AmocasW {
54                    rd,
55                    rs1,
56                    rs2,
57                    aq,
58                    rl,
59                })
60            }
61            // AMOCAS.D
62            (0b010_1111, 0b011, 0b00101) => {
63                let rd = Reg::from_bits(rd_bits)?;
64                let rs1 = Reg::from_bits(rs1_bits)?;
65                let rs2 = Reg::from_bits(rs2_bits)?;
66                let aq = (funct7 & 0b10) != 0;
67                let rl = (funct7 & 0b01) != 0;
68
69                Some(Self::AmocasD {
70                    rd,
71                    rs1,
72                    rs2,
73                    aq,
74                    rl,
75                })
76            }
77            // AMOCAS.Q, register-pair mode (RV64)
78            (0b010_1111, 0b100, 0b00101) => {
79                match (rd_bits & 1, rs2_bits & 1) {
80                    // Both halves of the register pairs must be even numbered, otherwise the
81                    // encoding is reserved
82                    (0, 0) => {
83                        let rs1 = Reg::from_bits(rs1_bits)?;
84                        let rd = Reg::from_bits(rd_bits)?;
85                        let rd_hi = Reg::from_bits(rd_bits + 1)?;
86                        let rs2 = Reg::from_bits(rs2_bits)?;
87                        let rs2_hi = Reg::from_bits(rs2_bits + 1)?;
88                        let aq = (funct7 & 0b10) != 0;
89                        let rl = (funct7 & 0b01) != 0;
90
91                        Some(Self::AmocasQ {
92                            rd,
93                            rs1,
94                            rs2,
95                            rd_hi,
96                            rs2_hi,
97                            aq,
98                            rl,
99                        })
100                    }
101                    _ => None,
102                }
103            }
104            _ => None,
105        }
106    }
107
108    #[inline(always)]
109    fn alignment() -> u8 {
110        align_of::<u32>() as u8
111    }
112
113    #[inline(always)]
114    fn size(&self) -> u8 {
115        size_of::<u32>() as u8
116    }
117}
118
119/// Format `aq`/`rl` suffix for display
120#[inline(always)]
121fn aq_rl_suffix(aq: &bool, rl: &bool) -> &'static str {
122    match (*aq, *rl) {
123        (false, false) => "",
124        (true, false) => ".aq",
125        (false, true) => ".rl",
126        (true, true) => ".aqrl",
127    }
128}
129
130#[instruction]
131impl<Reg> fmt::Display for Rv64ZacasInstruction<Reg>
132where
133    Reg: fmt::Display + Copy,
134{
135    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
136        #[rustfmt::skip]
137        match self {
138            Self::AmocasW { rd, rs1, rs2, aq, rl } => write!(f, "amocas.w{} {rd}, {rs2}, ({rs1})", aq_rl_suffix(aq, rl)),
139            Self::AmocasD { rd, rs1, rs2, aq, rl } => write!(f, "amocas.d{} {rd}, {rs2}, ({rs1})", aq_rl_suffix(aq, rl)),
140            Self::AmocasQ { rd, rs1, rs2, rd_hi, rs2_hi, aq, rl } => write!(f, "amocas.q{} {rd}, {rd_hi}, {rs2}, {rs2_hi}, ({rs1})", aq_rl_suffix(aq, rl)),
141        }
142    }
143}
ab_riscv_primitives/instructions/rv64/zacas.rs

ab_riscv_primitives/instructions/rv64/
zacas.rs
