ab_riscv_primitives/instructions/rv64/
zacas.rs

1//! RV64 Zacas extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::instructions::rv64::a::zaamo::Rv64ZaamoInstruction;
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12/// RISC-V RV64 Zacas instruction (Atomic Compare-and-Swap)
13#[instruction(inherit = [Rv64ZaamoInstruction])]
14#[derive(Debug, Clone, Copy)]
15#[derive_const(PartialEq, Eq)]
16#[rustfmt::skip]
17pub enum Rv64ZacasInstruction<Reg> {
18    /// Compare-and-swap word
19    AmocasW { rd: Reg, rs1: Reg, rs2: Reg, aq: bool, rl: bool },
20    /// Compare-and-swap doubleword
21    AmocasD { rd: Reg, rs1: Reg, rs2: Reg, aq: bool, rl: bool },
22    /// Compare-and-swap quadword, using register pairs `(rd, rd_hi)` and `(rs2, rs2_hi)` since
23    /// RV64 registers are only 64 bits wide.
24    AmocasQ { rd: Reg, rs1: Reg, rs2: Reg, rd_hi: Reg, rs2_hi: Reg, aq: bool, rl: bool },
25}
26
27#[instruction]
28const impl<Reg> Instruction for Rv64ZacasInstruction<Reg>
29where
30    Reg: [const] Register<Type = u64>,
31{
32    const ALIGNMENT: u8 = align_of::<u32>() as u8;
33
34    type Reg = Reg;
35
36    #[inline(always)]
37    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
38    fn try_decode(instruction: u32) -> Option<Self> {
39        let opcode = (instruction & 0b111_1111) as u8;
40        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
41        let funct3 = ((instruction >> 12) & 0b111) as u8;
42        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
43        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
44        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
45
46        match (opcode, funct3, funct7 >> 2) {
47            // AMOCAS.W
48            (0b010_1111, 0b010, 0b00101) => {
49                let rd = Reg::from_bits(rd_bits)?;
50                let rs1 = Reg::from_bits(rs1_bits)?;
51                let rs2 = Reg::from_bits(rs2_bits)?;
52                let aq = (funct7 & 0b10) != 0;
53                let rl = (funct7 & 0b01) != 0;
54
55                Some(Self::AmocasW {
56                    rd,
57                    rs1,
58                    rs2,
59                    aq,
60                    rl,
61                })
62            }
63            // AMOCAS.D
64            (0b010_1111, 0b011, 0b00101) => {
65                let rd = Reg::from_bits(rd_bits)?;
66                let rs1 = Reg::from_bits(rs1_bits)?;
67                let rs2 = Reg::from_bits(rs2_bits)?;
68                let aq = (funct7 & 0b10) != 0;
69                let rl = (funct7 & 0b01) != 0;
70
71                Some(Self::AmocasD {
72                    rd,
73                    rs1,
74                    rs2,
75                    aq,
76                    rl,
77                })
78            }
79            // AMOCAS.Q, register-pair mode (RV64)
80            (0b010_1111, 0b100, 0b00101) => {
81                match (rd_bits & 1, rs2_bits & 1) {
82                    // Both halves of the register pairs must be even numbered, otherwise the
83                    // encoding is reserved
84                    (0, 0) => {
85                        let rs1 = Reg::from_bits(rs1_bits)?;
86                        let rd = Reg::from_bits(rd_bits)?;
87                        let rd_hi = Reg::from_bits(rd_bits + 1)?;
88                        let rs2 = Reg::from_bits(rs2_bits)?;
89                        let rs2_hi = Reg::from_bits(rs2_bits + 1)?;
90                        let aq = (funct7 & 0b10) != 0;
91                        let rl = (funct7 & 0b01) != 0;
92
93                        Some(Self::AmocasQ {
94                            rd,
95                            rs1,
96                            rs2,
97                            rd_hi,
98                            rs2_hi,
99                            aq,
100                            rl,
101                        })
102                    }
103                    _ => None,
104                }
105            }
106            _ => None,
107        }
108    }
109
110    #[inline(always)]
111    fn size(&self) -> u8 {
112        size_of::<u32>() as u8
113    }
114}
115
116/// Format `aq`/`rl` suffix for display
117#[inline(always)]
118fn aq_rl_suffix(aq: &bool, rl: &bool) -> &'static str {
119    match (*aq, *rl) {
120        (false, false) => "",
121        (true, false) => ".aq",
122        (false, true) => ".rl",
123        (true, true) => ".aqrl",
124    }
125}
126
127#[instruction]
128impl<Reg> fmt::Display for Rv64ZacasInstruction<Reg>
129where
130    Reg: fmt::Display + Copy,
131{
132    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
133        #[rustfmt::skip]
134        match self {
135            Self::AmocasW { rd, rs1, rs2, aq, rl } => write!(f, "amocas.w{} {rd}, {rs2}, ({rs1})", aq_rl_suffix(aq, rl)),
136            Self::AmocasD { rd, rs1, rs2, aq, rl } => write!(f, "amocas.d{} {rd}, {rs2}, ({rs1})", aq_rl_suffix(aq, rl)),
137            Self::AmocasQ { rd, rs1, rs2, rd_hi, rs2_hi, aq, rl } => write!(f, "amocas.q{} {rd}, {rd_hi}, {rs2}, {rs2_hi}, ({rs1})", aq_rl_suffix(aq, rl)),
138        }
139    }
140}
ab_riscv_primitives/instructions/rv64/zacas.rs

ab_riscv_primitives/instructions/rv64/
zacas.rs
