ab_riscv_primitives/instructions/rv64/v/
zve64x.rs

1//! RV64 Zve64x extension (Vector Extension for Embedded Processors, ELEN=64, integer-only)
2
3mod arith;
4mod config;
5mod fixed_point;
6mod load;
7mod mask;
8mod muldiv;
9mod perm;
10mod reduction;
11mod store;
12mod widen_narrow;
13
14use crate::instructions::Instruction;
15use crate::instructions::rv64::v::zve64x::arith::Rv64Zve64xArithInstruction;
16use crate::instructions::rv64::v::zve64x::config::Rv64Zve64xConfigInstruction;
17use crate::instructions::rv64::v::zve64x::fixed_point::Rv64Zve64xFixedPointInstruction;
18use crate::instructions::rv64::v::zve64x::load::Rv64Zve64xLoadInstruction;
19use crate::instructions::rv64::v::zve64x::mask::Rv64Zve64xMaskInstruction;
20use crate::instructions::rv64::v::zve64x::muldiv::Rv64Zve64xMulDivInstruction;
21use crate::instructions::rv64::v::zve64x::perm::Rv64Zve64xPermInstruction;
22use crate::instructions::rv64::v::zve64x::reduction::Rv64Zve64xReductionInstruction;
23use crate::instructions::rv64::v::zve64x::store::Rv64Zve64xStoreInstruction;
24use crate::instructions::rv64::v::zve64x::widen_narrow::Rv64Zve64xWidenNarrowInstruction;
25use crate::registers::general_purpose::Register;
26use crate::registers::vector::{Eew, VReg};
27use ab_riscv_macros::instruction;
28use core::fmt;
29
30/// RISC-V RV64 Zve64x instruction
31#[instruction(
32    ignore = [Phantom],
33    inherit = [
34        Rv64Zve64xConfigInstruction,
35        Rv64Zve64xLoadInstruction,
36        Rv64Zve64xStoreInstruction,
37        Rv64Zve64xArithInstruction,
38        Rv64Zve64xMulDivInstruction,
39        Rv64Zve64xWidenNarrowInstruction,
40        Rv64Zve64xFixedPointInstruction,
41        Rv64Zve64xMaskInstruction,
42        Rv64Zve64xReductionInstruction,
43        Rv64Zve64xPermInstruction,
44    ],
45)]
46#[derive(Debug, Clone, Copy, PartialEq, Eq)]
47pub enum Rv64Zve64xInstruction<Reg> {}
48
49#[instruction]
50impl<Reg> const Instruction for Rv64Zve64xInstruction<Reg>
51where
52    Reg: [const] Register<Type = u64>,
53{
54    type Reg = Reg;
55
56    #[inline(always)]
57    fn try_decode(instruction: u32) -> Option<Self> {
58        None
59    }
60
61    #[inline(always)]
62    fn alignment() -> u8 {
63        size_of::<u32>() as u8
64    }
65
66    #[inline(always)]
67    fn size(&self) -> u8 {
68        size_of::<u32>() as u8
69    }
70}
71
72#[instruction]
73impl<Reg> fmt::Display for Rv64Zve64xInstruction<Reg>
74where
75    Reg: fmt::Display + Copy,
76{
77    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
78        match self {}
79    }
80}
ab_riscv_primitives/instructions/rv64/v/zve64x.rs

ab_riscv_primitives/instructions/rv64/v/
zve64x.rs
