ab_riscv_primitives/instructions/rv64/m/
zmmul.rs

1//! RV64 Zmmul extension (multiplication subset of M extension)
2
3#[cfg(test)]
4mod tests;
5
6use crate::hart::HartConfig;
7use crate::instructions::{ImplementedExtension, Instruction, IsaExtension};
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12/// RISC-V RV64 Zmmul instruction
13#[instruction]
14#[derive(Debug, Clone, Copy)]
15#[derive_const(PartialEq, Eq)]
16#[rustfmt::skip]
17pub enum Rv64ZmmulInstruction<Hart>
18where
19    Hart: HartConfig,
20{
21    Mul { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
22    Mulh { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
23    Mulhsu { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
24    Mulhu { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
25
26    // RV64 Zmmul instructions
27    Mulw { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
28}
29
30#[instruction]
31const impl<Reg, Hart> Instruction for Rv64ZmmulInstruction<Hart>
32where
33    Reg: [const] Register<Type = u64>,
34    Hart: [const] HartConfig<Reg = Reg>,
35{
36    const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = &[IsaExtension::new("zmmul", 1, 0)];
37
38    const ALIGNMENT: u8 = align_of::<u32>() as u8;
39
40    type Hart = Hart;
41
42    #[inline(always)]
43    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
44    fn try_decode(instruction: u32) -> Option<Self> {
45        let opcode = (instruction & 0b111_1111) as u8;
46        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
47        let funct3 = ((instruction >> 12) & 0b111) as u8;
48        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
49        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
50        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
51
52        match opcode {
53            // R-type
54            0b011_0011 => {
55                let rd = Reg::from_bits(rd_bits)?;
56                let rs1 = Reg::from_bits(rs1_bits)?;
57                let rs2 = Reg::from_bits(rs2_bits)?;
58                match (funct3, funct7) {
59                    (0b000, 0b000_0001) => Some(Self::Mul { rd, rs1, rs2 }),
60                    (0b001, 0b000_0001) => Some(Self::Mulh { rd, rs1, rs2 }),
61                    (0b010, 0b000_0001) => Some(Self::Mulhsu { rd, rs1, rs2 }),
62                    (0b011, 0b000_0001) => Some(Self::Mulhu { rd, rs1, rs2 }),
63                    _ => None,
64                }
65            }
66            // R-type W
67            0b011_1011 => {
68                let rd = Reg::from_bits(rd_bits)?;
69                let rs1 = Reg::from_bits(rs1_bits)?;
70                let rs2 = Reg::from_bits(rs2_bits)?;
71                match (funct3, funct7) {
72                    (0b000, 0b000_0001) => Some(Self::Mulw { rd, rs1, rs2 }),
73                    _ => None,
74                }
75            }
76            _ => None,
77        }
78    }
79
80    #[inline(always)]
81    fn size(&self) -> u8 {
82        size_of::<u32>() as u8
83    }
84}
85
86#[instruction]
87impl<Reg, Hart> fmt::Display for Rv64ZmmulInstruction<Hart>
88where
89    Reg: fmt::Display,
90    Hart: HartConfig<Reg = Reg>,
91{
92    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
93        match self {
94            Self::Mul { rd, rs1, rs2 } => write!(f, "mul {rd}, {rs1}, {rs2}"),
95            Self::Mulh { rd, rs1, rs2 } => write!(f, "mulh {rd}, {rs1}, {rs2}"),
96            Self::Mulhsu { rd, rs1, rs2 } => write!(f, "mulhsu {rd}, {rs1}, {rs2}"),
97            Self::Mulhu { rd, rs1, rs2 } => write!(f, "mulhu {rd}, {rs1}, {rs2}"),
98
99            Self::Mulw { rd, rs1, rs2 } => write!(f, "mulw {rd}, {rs1}, {rs2}"),
100        }
101    }
102}
ab_riscv_primitives/instructions/rv64/m/zmmul.rs

ab_riscv_primitives/instructions/rv64/m/
zmmul.rs
