ab_riscv_primitives/instructions/rv64/
m.rs

1//! RV64 M extension
2
3#[cfg(test)]
4mod tests;
5pub mod zmmul;
6
7use crate::instructions::Instruction;
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12/// RISC-V RV64 M instruction
13#[instruction]
14#[derive(Debug, Clone, Copy)]
15#[derive_const(PartialEq, Eq)]
16pub enum Rv64MInstruction<Reg> {
17    Mul { rd: Reg, rs1: Reg, rs2: Reg },
18    Mulh { rd: Reg, rs1: Reg, rs2: Reg },
19    Mulhsu { rd: Reg, rs1: Reg, rs2: Reg },
20    Mulhu { rd: Reg, rs1: Reg, rs2: Reg },
21    Div { rd: Reg, rs1: Reg, rs2: Reg },
22    Divu { rd: Reg, rs1: Reg, rs2: Reg },
23    Rem { rd: Reg, rs1: Reg, rs2: Reg },
24    Remu { rd: Reg, rs1: Reg, rs2: Reg },
25
26    // RV64M instructions
27    Mulw { rd: Reg, rs1: Reg, rs2: Reg },
28    Divw { rd: Reg, rs1: Reg, rs2: Reg },
29    Divuw { rd: Reg, rs1: Reg, rs2: Reg },
30    Remw { rd: Reg, rs1: Reg, rs2: Reg },
31    Remuw { rd: Reg, rs1: Reg, rs2: Reg },
32}
33
34#[instruction]
35const impl<Reg> Instruction for Rv64MInstruction<Reg>
36where
37    Reg: [const] Register<Type = u64>,
38{
39    type Reg = Reg;
40
41    #[inline(always)]
42    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
43    fn try_decode(instruction: u32) -> Option<Self> {
44        let opcode = (instruction & 0b111_1111) as u8;
45        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
46        let funct3 = ((instruction >> 12) & 0b111) as u8;
47        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
48        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
49        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
50
51        match opcode {
52            // R-type
53            0b011_0011 => {
54                let rd = Reg::from_bits(rd_bits)?;
55                let rs1 = Reg::from_bits(rs1_bits)?;
56                let rs2 = Reg::from_bits(rs2_bits)?;
57                match (funct3, funct7) {
58                    (0b000, 0b000_0001) => Some(Self::Mul { rd, rs1, rs2 }),
59                    (0b001, 0b000_0001) => Some(Self::Mulh { rd, rs1, rs2 }),
60                    (0b010, 0b000_0001) => Some(Self::Mulhsu { rd, rs1, rs2 }),
61                    (0b011, 0b000_0001) => Some(Self::Mulhu { rd, rs1, rs2 }),
62                    (0b100, 0b000_0001) => Some(Self::Div { rd, rs1, rs2 }),
63                    (0b101, 0b000_0001) => Some(Self::Divu { rd, rs1, rs2 }),
64                    (0b110, 0b000_0001) => Some(Self::Rem { rd, rs1, rs2 }),
65                    (0b111, 0b000_0001) => Some(Self::Remu { rd, rs1, rs2 }),
66                    _ => None,
67                }
68            }
69            // R-type W
70            0b011_1011 => {
71                let rd = Reg::from_bits(rd_bits)?;
72                let rs1 = Reg::from_bits(rs1_bits)?;
73                let rs2 = Reg::from_bits(rs2_bits)?;
74                match (funct3, funct7) {
75                    (0b000, 0b000_0001) => Some(Self::Mulw { rd, rs1, rs2 }),
76                    (0b100, 0b000_0001) => Some(Self::Divw { rd, rs1, rs2 }),
77                    (0b101, 0b000_0001) => Some(Self::Divuw { rd, rs1, rs2 }),
78                    (0b110, 0b000_0001) => Some(Self::Remw { rd, rs1, rs2 }),
79                    (0b111, 0b000_0001) => Some(Self::Remuw { rd, rs1, rs2 }),
80                    _ => None,
81                }
82            }
83            _ => None,
84        }
85    }
86
87    #[inline(always)]
88    fn alignment() -> u8 {
89        align_of::<u32>() as u8
90    }
91
92    #[inline(always)]
93    fn size(&self) -> u8 {
94        size_of::<u32>() as u8
95    }
96}
97
98#[instruction]
99impl<Reg> fmt::Display for Rv64MInstruction<Reg>
100where
101    Reg: fmt::Display,
102{
103    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
104        match self {
105            Self::Mul { rd, rs1, rs2 } => write!(f, "mul {rd}, {rs1}, {rs2}"),
106            Self::Mulh { rd, rs1, rs2 } => write!(f, "mulh {rd}, {rs1}, {rs2}"),
107            Self::Mulhsu { rd, rs1, rs2 } => write!(f, "mulhsu {rd}, {rs1}, {rs2}"),
108            Self::Mulhu { rd, rs1, rs2 } => write!(f, "mulhu {rd}, {rs1}, {rs2}"),
109            Self::Div { rd, rs1, rs2 } => write!(f, "div {rd}, {rs1}, {rs2}"),
110            Self::Divu { rd, rs1, rs2 } => write!(f, "divu {rd}, {rs1}, {rs2}"),
111            Self::Rem { rd, rs1, rs2 } => write!(f, "rem {rd}, {rs1}, {rs2}"),
112            Self::Remu { rd, rs1, rs2 } => write!(f, "remu {rd}, {rs1}, {rs2}"),
113
114            Self::Mulw { rd, rs1, rs2 } => write!(f, "mulw {rd}, {rs1}, {rs2}"),
115            Self::Divw { rd, rs1, rs2 } => write!(f, "divw {rd}, {rs1}, {rs2}"),
116            Self::Divuw { rd, rs1, rs2 } => write!(f, "divuw {rd}, {rs1}, {rs2}"),
117            Self::Remw { rd, rs1, rs2 } => write!(f, "remw {rd}, {rs1}, {rs2}"),
118            Self::Remuw { rd, rs1, rs2 } => write!(f, "remuw {rd}, {rs1}, {rs2}"),
119        }
120    }
121}
ab_riscv_primitives/instructions/rv64/m.rs

ab_riscv_primitives/instructions/rv64/
m.rs
