ab_riscv_primitives/instructions/rv64/
m.rs

1//! RV64 M extension
2
3#[cfg(test)]
4mod tests;
5pub mod zmmul;
6
7use crate::instructions::Instruction;
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12/// RISC-V RV64 M instruction
13#[instruction]
14#[derive(Debug, Clone, Copy)]
15#[derive_const(PartialEq, Eq)]
16pub enum Rv64MInstruction<Reg> {
17    Mul { rd: Reg, rs1: Reg, rs2: Reg },
18    Mulh { rd: Reg, rs1: Reg, rs2: Reg },
19    Mulhsu { rd: Reg, rs1: Reg, rs2: Reg },
20    Mulhu { rd: Reg, rs1: Reg, rs2: Reg },
21    Div { rd: Reg, rs1: Reg, rs2: Reg },
22    Divu { rd: Reg, rs1: Reg, rs2: Reg },
23    Rem { rd: Reg, rs1: Reg, rs2: Reg },
24    Remu { rd: Reg, rs1: Reg, rs2: Reg },
25
26    // RV64M instructions
27    Mulw { rd: Reg, rs1: Reg, rs2: Reg },
28    Divw { rd: Reg, rs1: Reg, rs2: Reg },
29    Divuw { rd: Reg, rs1: Reg, rs2: Reg },
30    Remw { rd: Reg, rs1: Reg, rs2: Reg },
31    Remuw { rd: Reg, rs1: Reg, rs2: Reg },
32}
33
34#[instruction]
35const impl<Reg> Instruction for Rv64MInstruction<Reg>
36where
37    Reg: [const] Register<Type = u64>,
38{
39    const ALIGNMENT: u8 = align_of::<u32>() as u8;
40
41    type Reg = Reg;
42
43    #[inline(always)]
44    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
45    fn try_decode(instruction: u32) -> Option<Self> {
46        let opcode = (instruction & 0b111_1111) as u8;
47        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
48        let funct3 = ((instruction >> 12) & 0b111) as u8;
49        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
50        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
51        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
52
53        match opcode {
54            // R-type
55            0b011_0011 => {
56                let rd = Reg::from_bits(rd_bits)?;
57                let rs1 = Reg::from_bits(rs1_bits)?;
58                let rs2 = Reg::from_bits(rs2_bits)?;
59                match (funct3, funct7) {
60                    (0b000, 0b000_0001) => Some(Self::Mul { rd, rs1, rs2 }),
61                    (0b001, 0b000_0001) => Some(Self::Mulh { rd, rs1, rs2 }),
62                    (0b010, 0b000_0001) => Some(Self::Mulhsu { rd, rs1, rs2 }),
63                    (0b011, 0b000_0001) => Some(Self::Mulhu { rd, rs1, rs2 }),
64                    (0b100, 0b000_0001) => Some(Self::Div { rd, rs1, rs2 }),
65                    (0b101, 0b000_0001) => Some(Self::Divu { rd, rs1, rs2 }),
66                    (0b110, 0b000_0001) => Some(Self::Rem { rd, rs1, rs2 }),
67                    (0b111, 0b000_0001) => Some(Self::Remu { rd, rs1, rs2 }),
68                    _ => None,
69                }
70            }
71            // R-type W
72            0b011_1011 => {
73                let rd = Reg::from_bits(rd_bits)?;
74                let rs1 = Reg::from_bits(rs1_bits)?;
75                let rs2 = Reg::from_bits(rs2_bits)?;
76                match (funct3, funct7) {
77                    (0b000, 0b000_0001) => Some(Self::Mulw { rd, rs1, rs2 }),
78                    (0b100, 0b000_0001) => Some(Self::Divw { rd, rs1, rs2 }),
79                    (0b101, 0b000_0001) => Some(Self::Divuw { rd, rs1, rs2 }),
80                    (0b110, 0b000_0001) => Some(Self::Remw { rd, rs1, rs2 }),
81                    (0b111, 0b000_0001) => Some(Self::Remuw { rd, rs1, rs2 }),
82                    _ => None,
83                }
84            }
85            _ => None,
86        }
87    }
88
89    #[inline(always)]
90    fn size(&self) -> u8 {
91        size_of::<u32>() as u8
92    }
93}
94
95#[instruction]
96impl<Reg> fmt::Display for Rv64MInstruction<Reg>
97where
98    Reg: fmt::Display,
99{
100    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
101        match self {
102            Self::Mul { rd, rs1, rs2 } => write!(f, "mul {rd}, {rs1}, {rs2}"),
103            Self::Mulh { rd, rs1, rs2 } => write!(f, "mulh {rd}, {rs1}, {rs2}"),
104            Self::Mulhsu { rd, rs1, rs2 } => write!(f, "mulhsu {rd}, {rs1}, {rs2}"),
105            Self::Mulhu { rd, rs1, rs2 } => write!(f, "mulhu {rd}, {rs1}, {rs2}"),
106            Self::Div { rd, rs1, rs2 } => write!(f, "div {rd}, {rs1}, {rs2}"),
107            Self::Divu { rd, rs1, rs2 } => write!(f, "divu {rd}, {rs1}, {rs2}"),
108            Self::Rem { rd, rs1, rs2 } => write!(f, "rem {rd}, {rs1}, {rs2}"),
109            Self::Remu { rd, rs1, rs2 } => write!(f, "remu {rd}, {rs1}, {rs2}"),
110
111            Self::Mulw { rd, rs1, rs2 } => write!(f, "mulw {rd}, {rs1}, {rs2}"),
112            Self::Divw { rd, rs1, rs2 } => write!(f, "divw {rd}, {rs1}, {rs2}"),
113            Self::Divuw { rd, rs1, rs2 } => write!(f, "divuw {rd}, {rs1}, {rs2}"),
114            Self::Remw { rd, rs1, rs2 } => write!(f, "remw {rd}, {rs1}, {rs2}"),
115            Self::Remuw { rd, rs1, rs2 } => write!(f, "remuw {rd}, {rs1}, {rs2}"),
116        }
117    }
118}
ab_riscv_primitives/instructions/rv64/m.rs

ab_riscv_primitives/instructions/rv64/
m.rs
