ab_riscv_primitives/instructions/rv64/
m.rs

1//! M extension
2
3#[cfg(test)]
4mod tests;
5pub mod zmmul;
6
7use crate::instructions::Instruction;
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12/// RISC-V RV64 M instruction
13#[instruction]
14#[derive(Debug, Clone, Copy, PartialEq, Eq)]
15pub enum Rv64MInstruction<Reg> {
16    Mul { rd: Reg, rs1: Reg, rs2: Reg },
17    Mulh { rd: Reg, rs1: Reg, rs2: Reg },
18    Mulhsu { rd: Reg, rs1: Reg, rs2: Reg },
19    Mulhu { rd: Reg, rs1: Reg, rs2: Reg },
20    Div { rd: Reg, rs1: Reg, rs2: Reg },
21    Divu { rd: Reg, rs1: Reg, rs2: Reg },
22    Rem { rd: Reg, rs1: Reg, rs2: Reg },
23    Remu { rd: Reg, rs1: Reg, rs2: Reg },
24
25    // RV64M instructions
26    Mulw { rd: Reg, rs1: Reg, rs2: Reg },
27    Divw { rd: Reg, rs1: Reg, rs2: Reg },
28    Divuw { rd: Reg, rs1: Reg, rs2: Reg },
29    Remw { rd: Reg, rs1: Reg, rs2: Reg },
30    Remuw { rd: Reg, rs1: Reg, rs2: Reg },
31}
32
33#[instruction]
34impl<Reg> const Instruction for Rv64MInstruction<Reg>
35where
36    Reg: [const] Register<Type = u64>,
37{
38    type Reg = Reg;
39
40    #[inline(always)]
41    fn try_decode(instruction: u32) -> Option<Self> {
42        let opcode = (instruction & 0b111_1111) as u8;
43        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
44        let funct3 = ((instruction >> 12) & 0b111) as u8;
45        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
46        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
47        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
48
49        match opcode {
50            // R-type
51            0b0110011 => {
52                let rd = Reg::from_bits(rd_bits)?;
53                let rs1 = Reg::from_bits(rs1_bits)?;
54                let rs2 = Reg::from_bits(rs2_bits)?;
55                match (funct3, funct7) {
56                    // M extension
57                    (0b000, 0b0000001) => Some(Self::Mul { rd, rs1, rs2 }),
58                    (0b001, 0b0000001) => Some(Self::Mulh { rd, rs1, rs2 }),
59                    (0b010, 0b0000001) => Some(Self::Mulhsu { rd, rs1, rs2 }),
60                    (0b011, 0b0000001) => Some(Self::Mulhu { rd, rs1, rs2 }),
61                    (0b100, 0b0000001) => Some(Self::Div { rd, rs1, rs2 }),
62                    (0b101, 0b0000001) => Some(Self::Divu { rd, rs1, rs2 }),
63                    (0b110, 0b0000001) => Some(Self::Rem { rd, rs1, rs2 }),
64                    (0b111, 0b0000001) => Some(Self::Remu { rd, rs1, rs2 }),
65                    _ => None,
66                }
67            }
68            // R-type W
69            0b0111011 => {
70                let rd = Reg::from_bits(rd_bits)?;
71                let rs1 = Reg::from_bits(rs1_bits)?;
72                let rs2 = Reg::from_bits(rs2_bits)?;
73                match (funct3, funct7) {
74                    (0b000, 0b0000001) => Some(Self::Mulw { rd, rs1, rs2 }),
75                    (0b100, 0b0000001) => Some(Self::Divw { rd, rs1, rs2 }),
76                    (0b101, 0b0000001) => Some(Self::Divuw { rd, rs1, rs2 }),
77                    (0b110, 0b0000001) => Some(Self::Remw { rd, rs1, rs2 }),
78                    (0b111, 0b0000001) => Some(Self::Remuw { rd, rs1, rs2 }),
79                    _ => None,
80                }
81            }
82            _ => None,
83        }
84    }
85
86    #[inline(always)]
87    fn alignment() -> u8 {
88        size_of::<u32>() as u8
89    }
90
91    #[inline(always)]
92    fn size(&self) -> u8 {
93        size_of::<u32>() as u8
94    }
95}
96
97impl<Reg> fmt::Display for Rv64MInstruction<Reg>
98where
99    Reg: fmt::Display,
100{
101    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
102        match self {
103            Self::Mul { rd, rs1, rs2 } => write!(f, "mul {}, {}, {}", rd, rs1, rs2),
104            Self::Mulh { rd, rs1, rs2 } => write!(f, "mulh {}, {}, {}", rd, rs1, rs2),
105            Self::Mulhsu { rd, rs1, rs2 } => write!(f, "mulhsu {}, {}, {}", rd, rs1, rs2),
106            Self::Mulhu { rd, rs1, rs2 } => write!(f, "mulhu {}, {}, {}", rd, rs1, rs2),
107            Self::Div { rd, rs1, rs2 } => write!(f, "div {}, {}, {}", rd, rs1, rs2),
108            Self::Divu { rd, rs1, rs2 } => write!(f, "divu {}, {}, {}", rd, rs1, rs2),
109            Self::Rem { rd, rs1, rs2 } => write!(f, "rem {}, {}, {}", rd, rs1, rs2),
110            Self::Remu { rd, rs1, rs2 } => write!(f, "remu {}, {}, {}", rd, rs1, rs2),
111
112            Self::Mulw { rd, rs1, rs2 } => write!(f, "mulw {}, {}, {}", rd, rs1, rs2),
113            Self::Divw { rd, rs1, rs2 } => write!(f, "divw {}, {}, {}", rd, rs1, rs2),
114            Self::Divuw { rd, rs1, rs2 } => write!(f, "divuw {}, {}, {}", rd, rs1, rs2),
115            Self::Remw { rd, rs1, rs2 } => write!(f, "remw {}, {}, {}", rd, rs1, rs2),
116            Self::Remuw { rd, rs1, rs2 } => write!(f, "remuw {}, {}, {}", rd, rs1, rs2),
117        }
118    }
119}
ab_riscv_primitives/instructions/rv64/m.rs

ab_riscv_primitives/instructions/rv64/
m.rs
