ab_riscv_primitives/instructions/rv64/c/
zca.rs

1//! RV64 Zca extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::instructions::utils::I24;
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12/// RISC-V RV64 Zca compressed instruction set
13#[instruction]
14#[derive(Debug, Clone, Copy)]
15#[derive_const(PartialEq, Eq)]
16#[rustfmt::skip]
17pub enum Rv64ZcaInstruction<Reg> {
18    // Quadrant 00
19    /// C.ADDI4SPN  rd' = sp + nzuimm  (nzuimm ∈ 4..1020 step 4)
20    CAddi4spn { rd: Reg, nzuimm: u16 },
21    /// C.LW  rd' = sext(mem32\[rs1' + uimm])
22    CLw { rd: Reg, rs1: Reg, uimm: u8 },
23    /// C.LD  rd' = mem64\[rs1' + uimm]
24    CLd { rd: Reg, rs1: Reg, uimm: u8 },
25    /// C.SW  mem32\[rs1' + uimm] = rs2'
26    CSw { rs1: Reg, rs2: Reg, uimm: u8 },
27    /// C.SD  mem64\[rs1' + uimm] = rs2'
28    CSd { rs1: Reg, rs2: Reg, uimm: u8 },
29
30    // Quadrant 01
31    /// C.NOP  (ADDI x0, x0, 0 with rd==x0 and nzimm==0)
32    CNop,
33    /// C.ADDI  rd += nzimm  (rd != x0)
34    CAddi { rd: Reg, nzimm: i8 },
35    /// C.ADDIW  rd = sext((rd\[31:0] + imm)\[31:0])  (rd != x0)
36    CAddiw { rd: Reg, imm: i8 },
37    /// C.LI  rd = sext(imm)  (rd=x0 is a HINT)
38    CLi { rd: Reg, imm: i8 },
39    /// C.ADDI16SP  sp += nzimm*16  (nzimm != 0)
40    CAddi16sp { nzimm: i16 },
41    /// C.LUI  rd = sext(nzimm << 12)  (rd != x0, rd != x2, nzimm != 0)
42    CLui { rd: Reg, nzimm: I24 },
43    /// C.SRLI  rd' >>= shamt  (logical right shift; shamt=0 with rd'=x0 is a HINT)
44    CSrli { rd: Reg, shamt: u8 },
45    /// C.SRAI  rd' >>= shamt  (arithmetic right shift; shamt=0 with rd'=x0 is a HINT)
46    CSrai { rd: Reg, shamt: u8 },
47    /// C.ANDI  rd' &= sext(imm)
48    CAndi { rd: Reg, imm: i8 },
49    /// C.SUB  rd' -= rs2'
50    CSub { rd: Reg, rs2: Reg },
51    /// C.XOR  rd' ^= rs2'
52    CXor { rd: Reg, rs2: Reg },
53    /// C.OR   rd' |= rs2'
54    COr { rd: Reg, rs2: Reg },
55    /// C.AND  rd' &= rs2'
56    CAnd { rd: Reg, rs2: Reg },
57    /// C.SUBW  rd' = sext((rd'\[31:0] - rs2'\[31:0])\[31:0])
58    CSubw { rd: Reg, rs2: Reg },
59    /// C.ADDW  rd' = sext((rd'\[31:0] + rs2'\[31:0])\[31:0])
60    CAddw { rd: Reg, rs2: Reg },
61    /// C.J  pc += sext(imm)
62    CJ { imm: i16 },
63    /// C.BEQZ  if rs1' == 0: pc += sext(imm)
64    CBeqz { rs1: Reg, imm: i16 },
65    /// C.BNEZ  if rs1' != 0: pc += sext(imm)
66    CBnez { rs1: Reg, imm: i16 },
67
68    // Quadrant 10
69    /// C.SLLI  rd <<= shamt  (rd=x0 or shamt=0 is a HINT)
70    CSlli { rd: Reg, shamt: u8 },
71    /// C.LWSP  rd = sext(mem32\[sp + uimm])  (rd != x0)
72    CLwsp { rd: Reg, uimm: u8 },
73    /// C.LDSP  rd = mem64\[sp + uimm]  (rd != x0)
74    CLdsp { rd: Reg, uimm: u16 },
75    /// C.JR  pc = rs1  (rs1 != x0)
76    CJr { rs1: Reg },
77    /// C.MV  rd = rs2  (rs2 != x0; rd=x0 is a HINT)
78    CMv { rd: Reg, rs2: Reg },
79    /// C.EBREAK
80    CEbreak,
81    /// C.JALR  ra = pc+2; pc = rs1  (rs1 != x0)
82    CJalr { rs1: Reg },
83    /// C.ADD  rd += rs2  (rs2 != x0; rd=x0 is a HINT)
84    CAdd { rd: Reg, rs2: Reg },
85    /// C.SWSP  mem32\[sp + uimm] = rs2
86    CSwsp { rs2: Reg, uimm: u8 },
87    /// C.SDSP  mem64\[sp + uimm] = rs2
88    CSdsp { rs2: Reg, uimm: u16 },
89
90    // Unimplemented/illegal
91    CUnimp,
92}
93
94#[instruction]
95const impl<Reg> Instruction for Rv64ZcaInstruction<Reg>
96where
97    Reg: [const] Register<Type = u64>,
98{
99    type Reg = Reg;
100
101    #[inline(always)]
102    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
103    fn try_decode(instruction: u32) -> Option<Self> {
104        /// Map a 3-bit "prime" register field to an absolute register number
105        #[inline(always)]
106        const fn prime_reg_bits(bits: u8) -> u8 {
107            bits + 8
108        }
109
110        /// Reconstruct the CB-type branch offset used by C.BEQZ / C.BNEZ.
111        ///
112        /// Bit layout in the 16-bit instruction word:
113        /// ```text
114        ///   imm[8]   = inst[12]
115        ///   imm[4:3] = inst[11:10]
116        ///   imm[7:6] = inst[6:5]
117        ///   imm[2:1] = inst[4:3]
118        ///   imm[5]   = inst[2]
119        /// imm[0] is always 0 (2-byte aligned).
120        /// ```
121        #[inline(always)]
122        const fn decode_cb_branch_imm(inst: u16) -> i16 {
123            let imm8 = ((inst >> 12u8) & 1).cast_signed();
124            let imm4_3 = ((inst >> 10u8) & 0b11).cast_signed();
125            let imm7_6 = ((inst >> 5u8) & 0b11).cast_signed();
126            let imm2_1 = ((inst >> 3u8) & 0b11).cast_signed();
127            let imm5 = ((inst >> 2u8) & 1).cast_signed();
128            let raw =
129                (imm8 << 8u8) | (imm7_6 << 6u8) | (imm5 << 5u8) | (imm4_3 << 3u8) | (imm2_1 << 1u8);
130            // Sign-extend from bit 8 (9-bit immediate -> i16)
131            (raw << 7u8) >> 7u8
132        }
133
134        /// Reconstruct the CJ-type jump offset used by C.J.
135        ///
136        /// Bit layout:
137        /// ```text
138        ///   imm[11]  = inst[12]
139        ///   imm[4]   = inst[11]
140        ///   imm[9:8] = inst[10:9]
141        ///   imm[10]  = inst[8]
142        ///   imm[6]   = inst[7]
143        ///   imm[7]   = inst[6]
144        ///   imm[3:1] = inst[5:3]
145        ///   imm[5]   = inst[2]
146        /// imm[0] is always 0 (2-byte aligned).
147        /// ```
148        #[inline(always)]
149        const fn decode_cj_imm(inst: u16) -> i16 {
150            let imm11 = ((inst >> 12u8) & 1).cast_signed();
151            let imm4 = ((inst >> 11u8) & 1).cast_signed();
152            let imm9_8 = ((inst >> 9u8) & 0b11).cast_signed();
153            let imm10 = ((inst >> 8u8) & 1).cast_signed();
154            let imm6 = ((inst >> 7u8) & 1).cast_signed();
155            let imm7 = ((inst >> 6u8) & 1).cast_signed();
156            let imm3_1 = ((inst >> 3u8) & 0b111).cast_signed();
157            let imm5 = ((inst >> 2u8) & 1).cast_signed();
158            let raw = (imm11 << 11u8)
159                | (imm10 << 10u8)
160                | (imm9_8 << 8u8)
161                | (imm7 << 7u8)
162                | (imm6 << 6u8)
163                | (imm5 << 5u8)
164                | (imm4 << 4u8)
165                | (imm3_1 << 1u8);
166            // Sign-extend from bit 11 (12-bit immediate -> i16)
167            (raw << 4u8) >> 4u8
168        }
169
170        let inst = instruction as u16;
171        let quadrant = inst & 0b11;
172        let funct3 = ((inst >> 13u8) & 0b111) as u8;
173
174        match quadrant {
175            // Quadrant 00
176            0b00 => match funct3 {
177                // C.ADDI4SPN
178                // nzuimm[5:4]  = inst[12:11]
179                // nzuimm[9:6]  = inst[10:7]
180                // nzuimm[2]    = inst[6]
181                // nzuimm[3]    = inst[5]
182                0b000 => {
183                    let imm5_4 = (inst >> 11u8) & 0b11;
184                    let imm9_6 = (inst >> 7u8) & 0xf;
185                    let imm2 = (inst >> 6u8) & 1;
186                    let imm3 = (inst >> 5u8) & 1;
187                    let nzuimm = (imm9_6 << 6u8) | (imm5_4 << 4u8) | (imm3 << 3u8) | (imm2 << 2u8);
188                    if nzuimm == 0 {
189                        if inst == 0 {
190                            Some(Self::CUnimp)
191                        } else {
192                            // Reserved encoding
193                            None
194                        }
195                    } else {
196                        let rd_bits = prime_reg_bits(((inst >> 2u8) & 0b111) as u8);
197                        let rd = Reg::from_bits(rd_bits)?;
198                        Some(Self::CAddi4spn { rd, nzuimm })
199                    }
200                }
201                // C.LW
202                // uimm[5:3] = inst[12:10], uimm[2] = inst[6], uimm[6] = inst[5]
203                0b010 => {
204                    let uimm5_3 = ((inst >> 10u8) & 0b111) as u8;
205                    let uimm2 = ((inst >> 6u8) & 1) as u8;
206                    let uimm6 = ((inst >> 5u8) & 1) as u8;
207                    let uimm = (uimm6 << 6u8) | (uimm5_3 << 3u8) | (uimm2 << 2u8);
208                    let rs1_bits = prime_reg_bits(((inst >> 7u8) & 0b111) as u8);
209                    let rd_bits = prime_reg_bits(((inst >> 2u8) & 0b111) as u8);
210                    let rs1 = Reg::from_bits(rs1_bits)?;
211                    let rd = Reg::from_bits(rd_bits)?;
212                    Some(Self::CLw { rd, rs1, uimm })
213                }
214                // C.LD
215                // uimm[5:3] = inst[12:10], uimm[7:6] = inst[6:5]
216                0b011 => {
217                    let uimm5_3 = ((inst >> 10u8) & 0b111) as u8;
218                    let uimm7_6 = ((inst >> 5u8) & 0b11) as u8;
219                    let uimm = (uimm7_6 << 6u8) | (uimm5_3 << 3u8);
220                    let rs1_bits = prime_reg_bits(((inst >> 7u8) & 0b111) as u8);
221                    let rd_bits = prime_reg_bits(((inst >> 2u8) & 0b111) as u8);
222                    let rs1 = Reg::from_bits(rs1_bits)?;
223                    let rd = Reg::from_bits(rd_bits)?;
224                    Some(Self::CLd { rd, rs1, uimm })
225                }
226                // C.SW  (same uimm layout as C.LW)
227                0b110 => {
228                    let uimm5_3 = ((inst >> 10u8) & 0b111) as u8;
229                    let uimm2 = ((inst >> 6u8) & 1) as u8;
230                    let uimm6 = ((inst >> 5u8) & 1) as u8;
231                    let uimm = (uimm6 << 6u8) | (uimm5_3 << 3u8) | (uimm2 << 2u8);
232                    let rs1_bits = prime_reg_bits(((inst >> 7u8) & 0b111) as u8);
233                    let rs2_bits = prime_reg_bits(((inst >> 2u8) & 0b111) as u8);
234                    let rs1 = Reg::from_bits(rs1_bits)?;
235                    let rs2 = Reg::from_bits(rs2_bits)?;
236                    Some(Self::CSw { rs1, rs2, uimm })
237                }
238                // C.SD (same uimm layout as C.LD)
239                0b111 => {
240                    let uimm5_3 = ((inst >> 10u8) & 0b111) as u8;
241                    let uimm7_6 = ((inst >> 5u8) & 0b11) as u8;
242                    let uimm = (uimm7_6 << 6u8) | (uimm5_3 << 3u8);
243                    let rs1_bits = prime_reg_bits(((inst >> 7u8) & 0b111) as u8);
244                    let rs2_bits = prime_reg_bits(((inst >> 2u8) & 0b111) as u8);
245                    let rs1 = Reg::from_bits(rs1_bits)?;
246                    let rs2 = Reg::from_bits(rs2_bits)?;
247                    Some(Self::CSd { rs1, rs2, uimm })
248                }
249                // funct3 = 001/100/101 are reserved in Zca Q00 (used by Zcb)
250                _ => None,
251            },
252
253            // Quadrant 01
254            0b01 => match funct3 {
255                // C.NOP (rd=x0) / C.ADDI (rd!=x0)
256                // nzimm[5] = inst[12], nzimm[4:0] = inst[6:2]
257                0b000 => {
258                    let rd_bits = ((inst >> 7u8) & 0x1f) as u8;
259                    let imm5 = ((inst >> 12u8) & 1) as u8;
260                    let imm4_0 = ((inst >> 2u8) & 0x1f) as u8;
261                    let imm_raw = (imm5 << 5u8) | imm4_0;
262                    // Sign-extend 6-bit immediate to i8
263                    let nzimm = ((imm_raw.cast_signed()) << 2u8) >> 2u8;
264                    if rd_bits == 0 && nzimm == 0 {
265                        Some(Self::CNop)
266                    } else {
267                        let rd = Reg::from_bits(rd_bits)?;
268                        Some(Self::CAddi { rd, nzimm })
269                    }
270                }
271                // C.ADDIW
272                // imm[5] = inst[12], imm[4:0] = inst[6:2]
273                0b001 => {
274                    let rd_bits = ((inst >> 7u8) & 0x1f) as u8;
275                    // rd=x0 is reserved
276                    if rd_bits == 0 {
277                        None?;
278                    }
279                    let rd = Reg::from_bits(rd_bits)?;
280                    let imm5 = ((inst >> 12u8) & 1) as u8;
281                    let imm4_0 = ((inst >> 2u8) & 0x1f) as u8;
282                    let imm_raw = (imm5 << 5u8) | imm4_0;
283                    let imm = ((imm_raw.cast_signed()) << 2u8) >> 2u8;
284                    Some(Self::CAddiw { rd, imm })
285                }
286                // C.LI  rd = sext(imm)  (rd=x0 is a HINT, still decoded)
287                // imm[5] = inst[12], imm[4:0] = inst[6:2]
288                0b010 => {
289                    let rd_bits = ((inst >> 7u8) & 0x1f) as u8;
290                    let rd = Reg::from_bits(rd_bits)?;
291                    let imm5 = ((inst >> 12u8) & 1) as u8;
292                    let imm4_0 = ((inst >> 2u8) & 0x1f) as u8;
293                    let imm_raw = (imm5 << 5u8) | imm4_0;
294                    let imm = ((imm_raw.cast_signed()) << 2u8) >> 2u8;
295                    Some(Self::CLi { rd, imm })
296                }
297                // C.ADDI16SP (rd=x2) / C.LUI (rd!=x0, rd!=x2)
298                0b011 => {
299                    let rd_bits = ((inst >> 7u8) & 0x1f) as u8;
300                    if rd_bits == 2 {
301                        // C.ADDI16SP
302                        // nzimm[9]   = inst[12]
303                        // nzimm[4]   = inst[6]
304                        // nzimm[6]   = inst[5]
305                        // nzimm[8:7] = inst[4:3]
306                        // nzimm[5]   = inst[2]
307                        let imm9 = ((inst >> 12u8) & 1).cast_signed();
308                        let imm4 = ((inst >> 6u8) & 1).cast_signed();
309                        let imm6 = ((inst >> 5u8) & 1).cast_signed();
310                        let imm8_7 = ((inst >> 3u8) & 0b11).cast_signed();
311                        let imm5 = ((inst >> 2u8) & 1).cast_signed();
312                        let raw = (imm9 << 9u8)
313                            | (imm8_7 << 7u8)
314                            | (imm6 << 6u8)
315                            | (imm5 << 5u8)
316                            | (imm4 << 4u8);
317                        if raw == 0 {
318                            None?;
319                        }
320                        // Sign-extend from bit 9 (10-bit nzimm -> i16)
321                        let nzimm = (raw << 6u8) >> 6u8;
322                        Some(Self::CAddi16sp { nzimm })
323                    } else {
324                        // C.LUI (rd=x0 is a hint, still decoded)
325                        let rd = Reg::from_bits(rd_bits)?;
326                        // nzimm[17]    = inst[12]
327                        // nzimm[16:12] = inst[6:2]
328                        let imm17 = ((inst >> 12u8) & 1) as i32;
329                        let imm16_12 = ((inst >> 2u8) & 0x1f) as i32;
330                        let raw = (imm17 << 17u8) | (imm16_12 << 12u8);
331                        if raw == 0 {
332                            None?;
333                        }
334                        // Sign-extend from bit 17 (18-bit nzimm -> i32)
335                        let nzimm = I24::from_i32((raw << 14u8) >> 14u8);
336                        Some(Self::CLui { rd, nzimm })
337                    }
338                }
339                // C.SRLI / C.SRAI / C.ANDI / arithmetic pairs
340                0b100 => {
341                    let funct2 = ((inst >> 10u8) & 0b11) as u8;
342                    let rd_bits = prime_reg_bits(((inst >> 7u8) & 0b111) as u8);
343                    match funct2 {
344                        // C.SRLI  shamt[5]=inst[12], shamt[4:0]=inst[6:2]
345                        // shamt=0 is a HINT, still decoded
346                        0b00 => {
347                            let rd = Reg::from_bits(rd_bits)?;
348                            let shamt5 = ((inst >> 12u8) & 1) as u8;
349                            let shamt40 = ((inst >> 2u8) & 0x1f) as u8;
350                            Some(Self::CSrli {
351                                rd,
352                                shamt: (shamt5 << 5u8) | shamt40,
353                            })
354                        }
355                        // C.SRAI  (same shamt layout as C.SRLI)
356                        // shamt=0 is a HINT, still decoded
357                        0b01 => {
358                            let rd = Reg::from_bits(rd_bits)?;
359                            let shamt5 = ((inst >> 12u8) & 1) as u8;
360                            let shamt40 = ((inst >> 2u8) & 0x1f) as u8;
361                            Some(Self::CSrai {
362                                rd,
363                                shamt: (shamt5 << 5u8) | shamt40,
364                            })
365                        }
366                        // C.ANDI  imm[5]=inst[12], imm[4:0]=inst[6:2]
367                        0b10 => {
368                            let rd = Reg::from_bits(rd_bits)?;
369                            let imm5 = ((inst >> 12u8) & 1) as u8;
370                            let imm4_0 = ((inst >> 2u8) & 0x1f) as u8;
371                            let imm_raw = (imm5 << 5u8) | imm4_0;
372                            let imm = ((imm_raw.cast_signed()) << 2u8) >> 2u8;
373                            Some(Self::CAndi { rd, imm })
374                        }
375                        // Arithmetic: sub-selected by inst[12] and inst[6:5]
376                        0b11 => {
377                            let bit12 = (inst >> 12u8) & 1;
378                            let funct2b = ((inst >> 5u8) & 0b11) as u8;
379                            let rs2_bits = prime_reg_bits(((inst >> 2u8) & 0b111) as u8);
380                            let rd = Reg::from_bits(rd_bits)?;
381                            let rs2 = Reg::from_bits(rs2_bits)?;
382                            if bit12 == 0 {
383                                match funct2b {
384                                    0b00 => Some(Self::CSub { rd, rs2 }),
385                                    0b01 => Some(Self::CXor { rd, rs2 }),
386                                    0b10 => Some(Self::COr { rd, rs2 }),
387                                    0b11 => Some(Self::CAnd { rd, rs2 }),
388                                    _ => None,
389                                }
390                            } else {
391                                // funct2b=10/11 reserved in Zca
392                                match funct2b {
393                                    0b00 => Some(Self::CSubw { rd, rs2 }),
394                                    0b01 => Some(Self::CAddw { rd, rs2 }),
395                                    // 10/11 used by Zcb
396                                    _ => None,
397                                }
398                            }
399                        }
400                        _ => None,
401                    }
402                }
403                // C.J
404                0b101 => Some(Self::CJ {
405                    imm: decode_cj_imm(inst),
406                }),
407                // C.BEQZ
408                0b110 => {
409                    let rs1_bits = prime_reg_bits(((inst >> 7u8) & 0b111) as u8);
410                    let rs1 = Reg::from_bits(rs1_bits)?;
411                    Some(Self::CBeqz {
412                        rs1,
413                        imm: decode_cb_branch_imm(inst),
414                    })
415                }
416                // C.BNEZ
417                0b111 => {
418                    let rs1_bits = prime_reg_bits(((inst >> 7u8) & 0b111) as u8);
419                    let rs1 = Reg::from_bits(rs1_bits)?;
420                    Some(Self::CBnez {
421                        rs1,
422                        imm: decode_cb_branch_imm(inst),
423                    })
424                }
425                _ => None,
426            },
427
428            // Quadrant 10
429            0b10 => match funct3 {
430                // C.SLLI  shamt[5]=inst[12], shamt[4:0]=inst[6:2]
431                // rd=x0 or shamt=0 is a HINT, still decoded
432                0b000 => {
433                    let rd_bits = ((inst >> 7u8) & 0x1f) as u8;
434                    let rd = Reg::from_bits(rd_bits)?;
435                    let shamt5 = ((inst >> 12u8) & 1) as u8;
436                    let shamt40 = ((inst >> 2u8) & 0x1f) as u8;
437                    Some(Self::CSlli {
438                        rd,
439                        shamt: (shamt5 << 5u8) | shamt40,
440                    })
441                }
442                // C.LWSP  uimm[5]=inst[12], uimm[4:2]=inst[6:4], uimm[7:6]=inst[3:2]
443                // rd=x0 is reserved
444                0b010 => {
445                    let rd_bits = ((inst >> 7u8) & 0x1f) as u8;
446                    if rd_bits == 0 {
447                        None?;
448                    }
449                    let rd = Reg::from_bits(rd_bits)?;
450                    let uimm5 = ((inst >> 12u8) & 1) as u8;
451                    let uimm42 = ((inst >> 4u8) & 0b111) as u8;
452                    let uimm76 = ((inst >> 2u8) & 0b11) as u8;
453                    let uimm = (uimm76 << 6u8) | (uimm5 << 5u8) | (uimm42 << 2u8);
454                    Some(Self::CLwsp { rd, uimm })
455                }
456                // C.LDSP  uimm[5]=inst[12], uimm[4:3]=inst[6:5], uimm[8:6]=inst[4:2]
457                // rd=x0 is reserved
458                0b011 => {
459                    let rd_bits = ((inst >> 7u8) & 0x1f) as u8;
460                    if rd_bits == 0 {
461                        None?;
462                    }
463                    let rd = Reg::from_bits(rd_bits)?;
464                    let uimm5 = (inst >> 12u8) & 1;
465                    let uimm43 = (inst >> 5u8) & 0b11;
466                    let uimm86 = (inst >> 2u8) & 0b111;
467                    let uimm = (uimm86 << 6u8) | (uimm5 << 5u8) | (uimm43 << 3u8);
468                    Some(Self::CLdsp { rd, uimm })
469                }
470                // C.JR / C.MV / C.EBREAK / C.JALR / C.ADD
471                0b100 => {
472                    let rs1_bits = ((inst >> 7u8) & 0x1f) as u8;
473                    let rs2_bits = ((inst >> 2u8) & 0x1f) as u8;
474                    let bit12 = (inst >> 12u8) & 1;
475                    if bit12 == 0 {
476                        if rs2_bits == 0 {
477                            // C.JR  (rs1=x0 is reserved)
478                            if rs1_bits == 0 {
479                                None?;
480                            }
481                            let rs1 = Reg::from_bits(rs1_bits)?;
482                            Some(Self::CJr { rs1 })
483                        } else {
484                            // C.MV  (rs2!=x0; rd=x0 is a HINT, still decoded)
485                            let rd = Reg::from_bits(rs1_bits)?;
486                            let rs2 = Reg::from_bits(rs2_bits)?;
487                            Some(Self::CMv { rd, rs2 })
488                        }
489                    } else if rs2_bits == 0 {
490                        if rs1_bits == 0 {
491                            // C.EBREAK
492                            Some(Self::CEbreak)
493                        } else {
494                            // C.JALR  (rs1!=x0)
495                            let rs1 = Reg::from_bits(rs1_bits)?;
496                            Some(Self::CJalr { rs1 })
497                        }
498                    } else {
499                        // C.ADD  (rs2!=x0; rd=x0 is a HINT, still decoded)
500                        let rd = Reg::from_bits(rs1_bits)?;
501                        let rs2 = Reg::from_bits(rs2_bits)?;
502                        Some(Self::CAdd { rd, rs2 })
503                    }
504                }
505                // C.SWSP  uimm[5:2]=inst[12:9], uimm[7:6]=inst[8:7]
506                0b110 => {
507                    let rs2_bits = ((inst >> 2u8) & 0x1f) as u8;
508                    let rs2 = Reg::from_bits(rs2_bits)?;
509                    let uimm52 = ((inst >> 9u8) & 0xf) as u8;
510                    let uimm76 = ((inst >> 7u8) & 0b11) as u8;
511                    let uimm = (uimm76 << 6u8) | (uimm52 << 2u8);
512                    Some(Self::CSwsp { rs2, uimm })
513                }
514                // C.SDSP  uimm[5:3]=inst[12:10], uimm[8:6]=inst[9:7]
515                0b111 => {
516                    let rs2_bits = ((inst >> 2u8) & 0x1f) as u8;
517                    let rs2 = Reg::from_bits(rs2_bits)?;
518                    let uimm53 = (inst >> 10u8) & 0b111;
519                    let uimm86 = (inst >> 7u8) & 0b111;
520                    let uimm = (uimm86 << 6u8) | (uimm53 << 3u8);
521                    Some(Self::CSdsp { rs2, uimm })
522                }
523                _ => None,
524            },
525
526            // Quadrant 11 = 32-bit instructions
527            _ => None,
528        }
529    }
530
531    #[inline(always)]
532    fn alignment() -> u8 {
533        align_of::<u16>() as u8
534    }
535
536    #[inline(always)]
537    fn size(&self) -> u8 {
538        size_of::<u16>() as u8
539    }
540}
541
542#[instruction]
543impl<Reg> fmt::Display for Rv64ZcaInstruction<Reg>
544where
545    Reg: fmt::Display,
546{
547    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
548        match self {
549            Self::CAddi4spn { rd, nzuimm } => write!(f, "c.addi4spn {rd}, sp, {nzuimm}"),
550            Self::CLw { rd, rs1, uimm } => write!(f, "c.lw {rd}, {uimm}({rs1})"),
551            Self::CLd { rd, rs1, uimm } => write!(f, "c.ld {rd}, {uimm}({rs1})"),
552            Self::CSw { rs1, rs2, uimm } => write!(f, "c.sw {rs2}, {uimm}({rs1})"),
553            Self::CSd { rs1, rs2, uimm } => write!(f, "c.sd {rs2}, {uimm}({rs1})"),
554            Self::CNop => write!(f, "c.nop"),
555            Self::CAddi { rd, nzimm } => write!(f, "c.addi {rd}, {nzimm}"),
556            Self::CAddiw { rd, imm } => write!(f, "c.addiw {rd}, {imm}"),
557            Self::CLi { rd, imm } => write!(f, "c.li {rd}, {imm}"),
558            Self::CAddi16sp { nzimm } => write!(f, "c.addi16sp sp, {nzimm}"),
559            Self::CLui { rd, nzimm } => write!(f, "c.lui {rd}, 0x{:x}", nzimm >> 12u8),
560            Self::CSrli { rd, shamt } => write!(f, "c.srli {rd}, {shamt}"),
561            Self::CSrai { rd, shamt } => write!(f, "c.srai {rd}, {shamt}"),
562            Self::CAndi { rd, imm } => write!(f, "c.andi {rd}, {imm}"),
563            Self::CSub { rd, rs2 } => write!(f, "c.sub {rd}, {rs2}"),
564            Self::CXor { rd, rs2 } => write!(f, "c.xor {rd}, {rs2}"),
565            Self::COr { rd, rs2 } => write!(f, "c.or {rd}, {rs2}"),
566            Self::CAnd { rd, rs2 } => write!(f, "c.and {rd}, {rs2}"),
567            Self::CSubw { rd, rs2 } => write!(f, "c.subw {rd}, {rs2}"),
568            Self::CAddw { rd, rs2 } => write!(f, "c.addw {rd}, {rs2}"),
569            Self::CJ { imm } => write!(f, "c.j {imm}"),
570            Self::CBeqz { rs1, imm } => write!(f, "c.beqz {rs1}, {imm}"),
571            Self::CBnez { rs1, imm } => write!(f, "c.bnez {rs1}, {imm}"),
572            Self::CSlli { rd, shamt } => write!(f, "c.slli {rd}, {shamt}"),
573            Self::CLwsp { rd, uimm } => write!(f, "c.lwsp {rd}, {uimm}(sp)"),
574            Self::CLdsp { rd, uimm } => write!(f, "c.ldsp {rd}, {uimm}(sp)"),
575            Self::CJr { rs1 } => write!(f, "c.jr {rs1}"),
576            Self::CMv { rd, rs2 } => write!(f, "c.mv {rd}, {rs2}"),
577            Self::CEbreak => write!(f, "c.ebreak"),
578            Self::CJalr { rs1 } => write!(f, "c.jalr {rs1}"),
579            Self::CAdd { rd, rs2 } => write!(f, "c.add {rd}, {rs2}"),
580            Self::CSwsp { rs2, uimm } => write!(f, "c.swsp {rs2}, {uimm}(sp)"),
581            Self::CSdsp { rs2, uimm } => write!(f, "c.sdsp {rs2}, {uimm}(sp)"),
582            Self::CUnimp => write!(f, "c.unimp"),
583        }
584    }
585}
ab_riscv_primitives/instructions/rv64/c/zca.rs

ab_riscv_primitives/instructions/rv64/c/
zca.rs
