ab_riscv_primitives/instructions/rv64/b/
zbs.rs

1//! RV64 Zbs extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::hart::HartConfig;
7use crate::instructions::utils::Shamt;
8use crate::instructions::{ImplementedExtension, Instruction, IsaExtension};
9use crate::registers::general_purpose::Register;
10use ab_riscv_macros::instruction;
11use core::fmt;
12
13/// RISC-V RV64 Zbs instruction (Single-bit instructions)
14#[instruction]
15#[derive(Debug, Clone, Copy)]
16#[derive_const(PartialEq, Eq)]
17#[rustfmt::skip]
18pub enum Rv64ZbsInstruction<Hart>
19where
20    Hart: HartConfig,
21{
22    // Single-Bit Set
23    Bset { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
24    Bseti { rd: Hart::Reg, rs1: Hart::Reg, shamt: Shamt<u64> },
25
26    // Single-Bit Clear
27    Bclr { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
28    Bclri { rd: Hart::Reg, rs1: Hart::Reg, shamt: Shamt<u64> },
29
30    // Single-Bit Invert
31    Binv { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
32    Binvi { rd: Hart::Reg, rs1: Hart::Reg, shamt: Shamt<u64> },
33
34    // Single-Bit Extract
35    Bext { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
36    Bexti { rd: Hart::Reg, rs1: Hart::Reg, shamt: Shamt<u64> },
37}
38
39#[instruction]
40const impl<Reg, Hart> Instruction for Rv64ZbsInstruction<Hart>
41where
42    Reg: [const] Register<Type = u64>,
43    Hart: [const] HartConfig<Reg = Reg>,
44{
45    const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = &[IsaExtension::new("zbs", 1, 0)];
46
47    const ALIGNMENT: u8 = align_of::<u32>() as u8;
48
49    type Hart = Hart;
50
51    #[inline(always)]
52    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
53    fn try_decode(instruction: u32) -> Option<Self> {
54        let opcode = (instruction & 0b111_1111) as u8;
55        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
56        let funct3 = ((instruction >> 12) & 0b111) as u8;
57        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
58        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
59        let shamt = Shamt::<u64>::new(((instruction >> 20) & 0x3f) as u8)?;
60        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
61        let funct6 = ((instruction >> 26) & 0b11_1111) as u8;
62
63        match opcode {
64            // R-type instructions
65            0b011_0011 => {
66                let rd = Reg::from_bits(rd_bits)?;
67                let rs1 = Reg::from_bits(rs1_bits)?;
68                let rs2 = Reg::from_bits(rs2_bits)?;
69                match (funct3, funct7) {
70                    (0b001, 0b001_0100) => Some(Self::Bset { rd, rs1, rs2 }),
71                    (0b001, 0b010_0100) => Some(Self::Bclr { rd, rs1, rs2 }),
72                    (0b001, 0b011_0100) => Some(Self::Binv { rd, rs1, rs2 }),
73                    (0b101, 0b010_0100) => Some(Self::Bext { rd, rs1, rs2 }),
74                    _ => None,
75                }
76            }
77            // I-type instructions
78            0b001_0011 => {
79                let rd = Reg::from_bits(rd_bits)?;
80                let rs1 = Reg::from_bits(rs1_bits)?;
81                match (funct3, funct6) {
82                    (0b001, 0b00_1010) => Some(Self::Bseti { rd, rs1, shamt }),
83                    (0b001, 0b01_0010) => Some(Self::Bclri { rd, rs1, shamt }),
84                    (0b001, 0b01_1010) => Some(Self::Binvi { rd, rs1, shamt }),
85                    (0b101, 0b01_0010) => Some(Self::Bexti { rd, rs1, shamt }),
86                    _ => None,
87                }
88            }
89            _ => None,
90        }
91    }
92
93    #[inline(always)]
94    fn size(&self) -> u8 {
95        size_of::<u32>() as u8
96    }
97}
98
99#[instruction]
100impl<Reg, Hart> fmt::Display for Rv64ZbsInstruction<Hart>
101where
102    Reg: fmt::Display,
103    Hart: HartConfig<Reg = Reg>,
104{
105    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
106        match self {
107            Self::Bset { rd, rs1, rs2 } => write!(f, "bset {rd}, {rs1}, {rs2}"),
108            Self::Bseti { rd, rs1, shamt } => write!(f, "bseti {rd}, {rs1}, {shamt}"),
109            Self::Bclr { rd, rs1, rs2 } => write!(f, "bclr {rd}, {rs1}, {rs2}"),
110            Self::Bclri { rd, rs1, shamt } => write!(f, "bclri {rd}, {rs1}, {shamt}"),
111            Self::Binv { rd, rs1, rs2 } => write!(f, "binv {rd}, {rs1}, {rs2}"),
112            Self::Binvi { rd, rs1, shamt } => write!(f, "binvi {rd}, {rs1}, {shamt}"),
113            Self::Bext { rd, rs1, rs2 } => write!(f, "bext {rd}, {rs1}, {rs2}"),
114            Self::Bexti { rd, rs1, shamt } => write!(f, "bexti {rd}, {rs1}, {shamt}"),
115        }
116    }
117}
ab_riscv_primitives/instructions/rv64/b/zbs.rs

ab_riscv_primitives/instructions/rv64/b/
zbs.rs
