ab_riscv_primitives/instructions/rv64/b/
zbs.rs

1//! RV64 Zbs extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11/// RISC-V RV64 Zbs instruction (Single-bit instructions)
12#[instruction]
13#[derive(Debug, Clone, Copy, PartialEq, Eq)]
14pub enum Rv64ZbsInstruction<Reg> {
15    // Single-Bit Set
16    Bset { rd: Reg, rs1: Reg, rs2: Reg },
17    Bseti { rd: Reg, rs1: Reg, shamt: u8 },
18
19    // Single-Bit Clear
20    Bclr { rd: Reg, rs1: Reg, rs2: Reg },
21    Bclri { rd: Reg, rs1: Reg, shamt: u8 },
22
23    // Single-Bit Invert
24    Binv { rd: Reg, rs1: Reg, rs2: Reg },
25    Binvi { rd: Reg, rs1: Reg, shamt: u8 },
26
27    // Single-Bit Extract
28    Bext { rd: Reg, rs1: Reg, rs2: Reg },
29    Bexti { rd: Reg, rs1: Reg, shamt: u8 },
30}
31
32#[instruction]
33const impl<Reg> Instruction for Rv64ZbsInstruction<Reg>
34where
35    Reg: [const] Register<Type = u64>,
36{
37    type Reg = Reg;
38
39    #[inline(always)]
40    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
41    fn try_decode(instruction: u32) -> Option<Self> {
42        let opcode = (instruction & 0b111_1111) as u8;
43        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
44        let funct3 = ((instruction >> 12) & 0b111) as u8;
45        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
46        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
47        let shamt = ((instruction >> 20) & 0x3f) as u8;
48        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
49        let funct6 = ((instruction >> 26) & 0b11_1111) as u8;
50
51        match opcode {
52            // R-type instructions
53            0b011_0011 => {
54                let rd = Reg::from_bits(rd_bits)?;
55                let rs1 = Reg::from_bits(rs1_bits)?;
56                let rs2 = Reg::from_bits(rs2_bits)?;
57                match (funct3, funct7) {
58                    (0b001, 0b001_0100) => Some(Self::Bset { rd, rs1, rs2 }),
59                    (0b001, 0b010_0100) => Some(Self::Bclr { rd, rs1, rs2 }),
60                    (0b001, 0b011_0100) => Some(Self::Binv { rd, rs1, rs2 }),
61                    (0b101, 0b010_0100) => Some(Self::Bext { rd, rs1, rs2 }),
62                    _ => None,
63                }
64            }
65            // I-type instructions
66            0b001_0011 => {
67                let rd = Reg::from_bits(rd_bits)?;
68                let rs1 = Reg::from_bits(rs1_bits)?;
69                match (funct3, funct6) {
70                    (0b001, 0b00_1010) => Some(Self::Bseti { rd, rs1, shamt }),
71                    (0b001, 0b01_0010) => Some(Self::Bclri { rd, rs1, shamt }),
72                    (0b001, 0b01_1010) => Some(Self::Binvi { rd, rs1, shamt }),
73                    (0b101, 0b01_0010) => Some(Self::Bexti { rd, rs1, shamt }),
74                    _ => None,
75                }
76            }
77            _ => None,
78        }
79    }
80
81    #[inline(always)]
82    fn alignment() -> u8 {
83        align_of::<u32>() as u8
84    }
85
86    #[inline(always)]
87    fn size(&self) -> u8 {
88        size_of::<u32>() as u8
89    }
90}
91
92#[instruction]
93impl<Reg> fmt::Display for Rv64ZbsInstruction<Reg>
94where
95    Reg: fmt::Display,
96{
97    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
98        match self {
99            Self::Bset { rd, rs1, rs2 } => write!(f, "bset {rd}, {rs1}, {rs2}"),
100            Self::Bseti { rd, rs1, shamt } => write!(f, "bseti {rd}, {rs1}, {shamt}"),
101            Self::Bclr { rd, rs1, rs2 } => write!(f, "bclr {rd}, {rs1}, {rs2}"),
102            Self::Bclri { rd, rs1, shamt } => write!(f, "bclri {rd}, {rs1}, {shamt}"),
103            Self::Binv { rd, rs1, rs2 } => write!(f, "binv {rd}, {rs1}, {rs2}"),
104            Self::Binvi { rd, rs1, shamt } => write!(f, "binvi {rd}, {rs1}, {shamt}"),
105            Self::Bext { rd, rs1, rs2 } => write!(f, "bext {rd}, {rs1}, {rs2}"),
106            Self::Bexti { rd, rs1, shamt } => write!(f, "bexti {rd}, {rs1}, {shamt}"),
107        }
108    }
109}
ab_riscv_primitives/instructions/rv64/b/zbs.rs

ab_riscv_primitives/instructions/rv64/b/
zbs.rs
