ab_riscv_primitives/instructions/rv64/b/
zbc.rs1#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11#[instruction]
13#[derive(Debug, Clone, Copy, PartialEq, Eq)]
14pub enum Rv64ZbcInstruction<Reg> {
15 Clmul { rd: Reg, rs1: Reg, rs2: Reg },
16 Clmulh { rd: Reg, rs1: Reg, rs2: Reg },
17 Clmulr { rd: Reg, rs1: Reg, rs2: Reg },
18}
19
20#[instruction]
21impl<Reg> const Instruction for Rv64ZbcInstruction<Reg>
22where
23 Reg: [const] Register<Type = u64>,
24{
25 type Reg = Reg;
26
27 #[inline(always)]
28 fn try_decode(instruction: u32) -> Option<Self> {
29 let opcode = (instruction & 0b111_1111) as u8;
30 let rd_bits = ((instruction >> 7) & 0x1f) as u8;
31 let funct3 = ((instruction >> 12) & 0b111) as u8;
32 let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
33 let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
34 let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
35
36 match opcode {
37 0b0110011 => {
39 let rd = Reg::from_bits(rd_bits)?;
40 let rs1 = Reg::from_bits(rs1_bits)?;
41 let rs2 = Reg::from_bits(rs2_bits)?;
42 match (funct3, funct7) {
43 (0b001, 0b0000101) => Some(Self::Clmul { rd, rs1, rs2 }),
44 (0b011, 0b0000101) => Some(Self::Clmulh { rd, rs1, rs2 }),
45 (0b010, 0b0000101) => Some(Self::Clmulr { rd, rs1, rs2 }),
46 _ => None,
47 }
48 }
49 _ => None,
50 }
51 }
52
53 #[inline(always)]
54 fn alignment() -> u8 {
55 size_of::<u32>() as u8
56 }
57
58 #[inline(always)]
59 fn size(&self) -> u8 {
60 size_of::<u32>() as u8
61 }
62}
63
64impl<Reg> fmt::Display for Rv64ZbcInstruction<Reg>
65where
66 Reg: fmt::Display,
67{
68 fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
69 match self {
70 Self::Clmul { rd, rs1, rs2 } => write!(f, "clmul {}, {}, {}", rd, rs1, rs2),
71 Self::Clmulh { rd, rs1, rs2 } => write!(f, "clmulh {}, {}, {}", rd, rs1, rs2),
72 Self::Clmulr { rd, rs1, rs2 } => write!(f, "clmulr {}, {}, {}", rd, rs1, rs2),
73 }
74 }
75}