ab_riscv_primitives/instructions/rv64/b/
zba.rs

1//! RV64 Zba extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11/// RISC-V RV64 Zba instruction (Address generation)
12#[instruction]
13#[derive(Debug, Clone, Copy, PartialEq, Eq)]
14pub enum Rv64ZbaInstruction<Reg> {
15    AddUw { rd: Reg, rs1: Reg, rs2: Reg },
16    Sh1add { rd: Reg, rs1: Reg, rs2: Reg },
17    Sh1addUw { rd: Reg, rs1: Reg, rs2: Reg },
18    Sh2add { rd: Reg, rs1: Reg, rs2: Reg },
19    Sh2addUw { rd: Reg, rs1: Reg, rs2: Reg },
20    Sh3add { rd: Reg, rs1: Reg, rs2: Reg },
21    Sh3addUw { rd: Reg, rs1: Reg, rs2: Reg },
22    SlliUw { rd: Reg, rs1: Reg, shamt: u8 },
23}
24
25#[instruction]
26impl<Reg> const Instruction for Rv64ZbaInstruction<Reg>
27where
28    Reg: [const] Register<Type = u64>,
29{
30    type Reg = Reg;
31
32    #[inline(always)]
33    fn try_decode(instruction: u32) -> Option<Self> {
34        let opcode = (instruction & 0b111_1111) as u8;
35        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
36        let funct3 = ((instruction >> 12) & 0b111) as u8;
37        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
38        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
39        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
40        let funct6 = ((instruction >> 26) & 0b11_1111) as u8;
41
42        match opcode {
43            // R-type
44            0b0110011 => {
45                let rd = Reg::from_bits(rd_bits)?;
46                let rs1 = Reg::from_bits(rs1_bits)?;
47                let rs2 = Reg::from_bits(rs2_bits)?;
48                match (funct3, funct7) {
49                    (0b010, 0b0010000) => Some(Self::Sh1add { rd, rs1, rs2 }),
50                    (0b100, 0b0010000) => Some(Self::Sh2add { rd, rs1, rs2 }),
51                    (0b110, 0b0010000) => Some(Self::Sh3add { rd, rs1, rs2 }),
52                    _ => None,
53                }
54            }
55            // R-type W
56            0b0111011 => {
57                let rd = Reg::from_bits(rd_bits)?;
58                let rs1 = Reg::from_bits(rs1_bits)?;
59                match funct3 {
60                    0b000 => {
61                        let rs2 = Reg::from_bits(rs2_bits)?;
62                        match funct7 {
63                            0b0000100 => Some(Self::AddUw { rd, rs1, rs2 }),
64                            _ => None,
65                        }
66                    }
67                    0b001 => {
68                        let shamt = rs2_bits;
69                        match funct6 {
70                            0b000010 => Some(Self::SlliUw { rd, rs1, shamt }),
71                            _ => None,
72                        }
73                    }
74                    0b010 => {
75                        let rs2 = Reg::from_bits(rs2_bits)?;
76                        match funct7 {
77                            0b0010000 => Some(Self::Sh1addUw { rd, rs1, rs2 }),
78                            _ => None,
79                        }
80                    }
81                    0b100 => {
82                        let rs2 = Reg::from_bits(rs2_bits)?;
83                        match funct7 {
84                            0b0010000 => Some(Self::Sh2addUw { rd, rs1, rs2 }),
85                            _ => None,
86                        }
87                    }
88                    0b110 => {
89                        let rs2 = Reg::from_bits(rs2_bits)?;
90                        match funct7 {
91                            0b0010000 => Some(Self::Sh3addUw { rd, rs1, rs2 }),
92                            _ => None,
93                        }
94                    }
95                    _ => None,
96                }
97            }
98            _ => None,
99        }
100    }
101
102    #[inline(always)]
103    fn alignment() -> u8 {
104        size_of::<u32>() as u8
105    }
106
107    #[inline(always)]
108    fn size(&self) -> u8 {
109        size_of::<u32>() as u8
110    }
111}
112
113impl<Reg> fmt::Display for Rv64ZbaInstruction<Reg>
114where
115    Reg: fmt::Display,
116{
117    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
118        match self {
119            Self::AddUw { rd, rs1, rs2 } => write!(f, "add.uw {}, {}, {}", rd, rs1, rs2),
120            Self::Sh1add { rd, rs1, rs2 } => write!(f, "sh1add {}, {}, {}", rd, rs1, rs2),
121            Self::Sh1addUw { rd, rs1, rs2 } => write!(f, "sh1add.uw {}, {}, {}", rd, rs1, rs2),
122            Self::Sh2add { rd, rs1, rs2 } => write!(f, "sh2add {}, {}, {}", rd, rs1, rs2),
123            Self::Sh2addUw { rd, rs1, rs2 } => write!(f, "sh2add.uw {}, {}, {}", rd, rs1, rs2),
124            Self::Sh3add { rd, rs1, rs2 } => write!(f, "sh3add {}, {}, {}", rd, rs1, rs2),
125            Self::Sh3addUw { rd, rs1, rs2 } => write!(f, "sh3add.uw {}, {}, {}", rd, rs1, rs2),
126            Self::SlliUw { rd, rs1, shamt } => write!(f, "slli.uw {}, {}, {}", rd, rs1, shamt),
127        }
128    }
129}
ab_riscv_primitives/instructions/rv64/b/zba.rs

ab_riscv_primitives/instructions/rv64/b/
zba.rs
