ab_riscv_primitives/instructions/rv64/b/
zba.rs

1//! RV64 Zba extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11/// RISC-V RV64 Zba instruction (Address generation)
12#[instruction]
13#[derive(Debug, Clone, Copy, PartialEq, Eq)]
14pub enum Rv64ZbaInstruction<Reg> {
15    AddUw { rd: Reg, rs1: Reg, rs2: Reg },
16    Sh1add { rd: Reg, rs1: Reg, rs2: Reg },
17    Sh1addUw { rd: Reg, rs1: Reg, rs2: Reg },
18    Sh2add { rd: Reg, rs1: Reg, rs2: Reg },
19    Sh2addUw { rd: Reg, rs1: Reg, rs2: Reg },
20    Sh3add { rd: Reg, rs1: Reg, rs2: Reg },
21    Sh3addUw { rd: Reg, rs1: Reg, rs2: Reg },
22    SlliUw { rd: Reg, rs1: Reg, shamt: u8 },
23}
24
25#[instruction]
26const impl<Reg> Instruction for Rv64ZbaInstruction<Reg>
27where
28    Reg: [const] Register<Type = u64>,
29{
30    type Reg = Reg;
31
32    #[inline(always)]
33    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
34    fn try_decode(instruction: u32) -> Option<Self> {
35        let opcode = (instruction & 0b111_1111) as u8;
36        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
37        let funct3 = ((instruction >> 12) & 0b111) as u8;
38        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
39        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
40        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
41        let funct6 = ((instruction >> 26) & 0b11_1111) as u8;
42
43        match opcode {
44            // R-type
45            0b011_0011 => {
46                let rd = Reg::from_bits(rd_bits)?;
47                let rs1 = Reg::from_bits(rs1_bits)?;
48                let rs2 = Reg::from_bits(rs2_bits)?;
49                match (funct3, funct7) {
50                    (0b010, 0b001_0000) => Some(Self::Sh1add { rd, rs1, rs2 }),
51                    (0b100, 0b001_0000) => Some(Self::Sh2add { rd, rs1, rs2 }),
52                    (0b110, 0b001_0000) => Some(Self::Sh3add { rd, rs1, rs2 }),
53                    _ => None,
54                }
55            }
56            // I-type W (OP-IMM-32)
57            0b001_1011 => {
58                let rd = Reg::from_bits(rd_bits)?;
59                let rs1 = Reg::from_bits(rs1_bits)?;
60                // shamt is 6 bits: [25:20]
61                let shamt = ((instruction >> 20) & 0x3f) as u8;
62                match (funct3, funct6) {
63                    (0b001, 0b00_0010) => Some(Self::SlliUw { rd, rs1, shamt }),
64                    _ => None,
65                }
66            }
67            // R-type W (OP-32)
68            0b011_1011 => {
69                let rd = Reg::from_bits(rd_bits)?;
70                let rs1 = Reg::from_bits(rs1_bits)?;
71                match funct3 {
72                    0b000 => {
73                        let rs2 = Reg::from_bits(rs2_bits)?;
74                        match funct7 {
75                            0b000_0100 => Some(Self::AddUw { rd, rs1, rs2 }),
76                            _ => None,
77                        }
78                    }
79                    0b010 => {
80                        let rs2 = Reg::from_bits(rs2_bits)?;
81                        match funct7 {
82                            0b001_0000 => Some(Self::Sh1addUw { rd, rs1, rs2 }),
83                            _ => None,
84                        }
85                    }
86                    0b100 => {
87                        let rs2 = Reg::from_bits(rs2_bits)?;
88                        match funct7 {
89                            0b001_0000 => Some(Self::Sh2addUw { rd, rs1, rs2 }),
90                            _ => None,
91                        }
92                    }
93                    0b110 => {
94                        let rs2 = Reg::from_bits(rs2_bits)?;
95                        match funct7 {
96                            0b001_0000 => Some(Self::Sh3addUw { rd, rs1, rs2 }),
97                            _ => None,
98                        }
99                    }
100                    _ => None,
101                }
102            }
103            _ => None,
104        }
105    }
106
107    #[inline(always)]
108    fn alignment() -> u8 {
109        align_of::<u32>() as u8
110    }
111
112    #[inline(always)]
113    fn size(&self) -> u8 {
114        size_of::<u32>() as u8
115    }
116}
117
118#[instruction]
119impl<Reg> fmt::Display for Rv64ZbaInstruction<Reg>
120where
121    Reg: fmt::Display,
122{
123    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
124        match self {
125            Self::AddUw { rd, rs1, rs2 } => write!(f, "add.uw {rd}, {rs1}, {rs2}"),
126            Self::Sh1add { rd, rs1, rs2 } => write!(f, "sh1add {rd}, {rs1}, {rs2}"),
127            Self::Sh1addUw { rd, rs1, rs2 } => write!(f, "sh1add.uw {rd}, {rs1}, {rs2}"),
128            Self::Sh2add { rd, rs1, rs2 } => write!(f, "sh2add {rd}, {rs1}, {rs2}"),
129            Self::Sh2addUw { rd, rs1, rs2 } => write!(f, "sh2add.uw {rd}, {rs1}, {rs2}"),
130            Self::Sh3add { rd, rs1, rs2 } => write!(f, "sh3add {rd}, {rs1}, {rs2}"),
131            Self::Sh3addUw { rd, rs1, rs2 } => write!(f, "sh3add.uw {rd}, {rs1}, {rs2}"),
132            Self::SlliUw { rd, rs1, shamt } => write!(f, "slli.uw {rd}, {rs1}, {shamt}"),
133        }
134    }
135}
ab_riscv_primitives/instructions/rv64/b/zba.rs

ab_riscv_primitives/instructions/rv64/b/
zba.rs
