ab_riscv_primitives/instructions/rv64/b/
zba.rs

1//! RV64 Zba extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11/// RISC-V RV64 Zba instruction (Address generation)
12#[instruction]
13#[derive(Debug, Clone, Copy, PartialEq, Eq)]
14pub enum Rv64ZbaInstruction<Reg> {
15    AddUw { rd: Reg, rs1: Reg, rs2: Reg },
16    Sh1add { rd: Reg, rs1: Reg, rs2: Reg },
17    Sh1addUw { rd: Reg, rs1: Reg, rs2: Reg },
18    Sh2add { rd: Reg, rs1: Reg, rs2: Reg },
19    Sh2addUw { rd: Reg, rs1: Reg, rs2: Reg },
20    Sh3add { rd: Reg, rs1: Reg, rs2: Reg },
21    Sh3addUw { rd: Reg, rs1: Reg, rs2: Reg },
22    SlliUw { rd: Reg, rs1: Reg, shamt: u8 },
23}
24
25#[instruction]
26impl<Reg> const Instruction for Rv64ZbaInstruction<Reg>
27where
28    Reg: [const] Register<Type = u64>,
29{
30    type Reg = Reg;
31
32    #[inline(always)]
33    fn try_decode(instruction: u32) -> Option<Self> {
34        let opcode = (instruction & 0b111_1111) as u8;
35        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
36        let funct3 = ((instruction >> 12) & 0b111) as u8;
37        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
38        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
39        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
40        let funct6 = ((instruction >> 26) & 0b11_1111) as u8;
41
42        match opcode {
43            // R-type
44            0b0110011 => {
45                let rd = Reg::from_bits(rd_bits)?;
46                let rs1 = Reg::from_bits(rs1_bits)?;
47                let rs2 = Reg::from_bits(rs2_bits)?;
48                match (funct3, funct7) {
49                    (0b010, 0b0010000) => Some(Self::Sh1add { rd, rs1, rs2 }),
50                    (0b100, 0b0010000) => Some(Self::Sh2add { rd, rs1, rs2 }),
51                    (0b110, 0b0010000) => Some(Self::Sh3add { rd, rs1, rs2 }),
52                    _ => None,
53                }
54            }
55            // I-type W (OP-IMM-32)
56            0b0011011 => {
57                let rd = Reg::from_bits(rd_bits)?;
58                let rs1 = Reg::from_bits(rs1_bits)?;
59                // shamt is 6 bits: [25:20]
60                let shamt = ((instruction >> 20) & 0x3f) as u8;
61                match (funct3, funct6) {
62                    (0b001, 0b000010) => Some(Self::SlliUw { rd, rs1, shamt }),
63                    _ => None,
64                }
65            }
66            // R-type W (OP-32)
67            0b0111011 => {
68                let rd = Reg::from_bits(rd_bits)?;
69                let rs1 = Reg::from_bits(rs1_bits)?;
70                match funct3 {
71                    0b000 => {
72                        let rs2 = Reg::from_bits(rs2_bits)?;
73                        match funct7 {
74                            0b0000100 => Some(Self::AddUw { rd, rs1, rs2 }),
75                            _ => None,
76                        }
77                    }
78                    0b010 => {
79                        let rs2 = Reg::from_bits(rs2_bits)?;
80                        match funct7 {
81                            0b0010000 => Some(Self::Sh1addUw { rd, rs1, rs2 }),
82                            _ => None,
83                        }
84                    }
85                    0b100 => {
86                        let rs2 = Reg::from_bits(rs2_bits)?;
87                        match funct7 {
88                            0b0010000 => Some(Self::Sh2addUw { rd, rs1, rs2 }),
89                            _ => None,
90                        }
91                    }
92                    0b110 => {
93                        let rs2 = Reg::from_bits(rs2_bits)?;
94                        match funct7 {
95                            0b0010000 => Some(Self::Sh3addUw { rd, rs1, rs2 }),
96                            _ => None,
97                        }
98                    }
99                    _ => None,
100                }
101            }
102            _ => None,
103        }
104    }
105
106    #[inline(always)]
107    fn alignment() -> u8 {
108        size_of::<u32>() as u8
109    }
110
111    #[inline(always)]
112    fn size(&self) -> u8 {
113        size_of::<u32>() as u8
114    }
115}
116
117impl<Reg> fmt::Display for Rv64ZbaInstruction<Reg>
118where
119    Reg: fmt::Display,
120{
121    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
122        match self {
123            Self::AddUw { rd, rs1, rs2 } => write!(f, "add.uw {}, {}, {}", rd, rs1, rs2),
124            Self::Sh1add { rd, rs1, rs2 } => write!(f, "sh1add {}, {}, {}", rd, rs1, rs2),
125            Self::Sh1addUw { rd, rs1, rs2 } => write!(f, "sh1add.uw {}, {}, {}", rd, rs1, rs2),
126            Self::Sh2add { rd, rs1, rs2 } => write!(f, "sh2add {}, {}, {}", rd, rs1, rs2),
127            Self::Sh2addUw { rd, rs1, rs2 } => write!(f, "sh2add.uw {}, {}, {}", rd, rs1, rs2),
128            Self::Sh3add { rd, rs1, rs2 } => write!(f, "sh3add {}, {}, {}", rd, rs1, rs2),
129            Self::Sh3addUw { rd, rs1, rs2 } => write!(f, "sh3add.uw {}, {}, {}", rd, rs1, rs2),
130            Self::SlliUw { rd, rs1, shamt } => write!(f, "slli.uw {}, {}, {}", rd, rs1, shamt),
131        }
132    }
133}
ab_riscv_primitives/instructions/rv64/b/zba.rs

ab_riscv_primitives/instructions/rv64/b/
zba.rs
