ab_riscv_primitives/instructions/rv64/b/
zba.rs

1//! RV64 Zba extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::hart::HartConfig;
7use crate::instructions::utils::Shamt;
8use crate::instructions::{ImplementedExtension, Instruction, IsaExtension};
9use crate::registers::general_purpose::Register;
10use ab_riscv_macros::instruction;
11use core::fmt;
12
13/// RISC-V RV64 Zba instruction (Address generation)
14#[instruction]
15#[derive(Debug, Clone, Copy)]
16#[derive_const(PartialEq, Eq)]
17#[rustfmt::skip]
18pub enum Rv64ZbaInstruction<Hart>
19where
20    Hart: HartConfig,
21{
22    AddUw { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
23    Sh1add { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
24    Sh1addUw { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
25    Sh2add { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
26    Sh2addUw { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
27    Sh3add { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
28    Sh3addUw { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
29    SlliUw { rd: Hart::Reg, rs1: Hart::Reg, shamt: Shamt<u64> },
30}
31
32#[instruction]
33const impl<Reg, Hart> Instruction for Rv64ZbaInstruction<Hart>
34where
35    Reg: [const] Register<Type = u64>,
36    Hart: [const] HartConfig<Reg = Reg>,
37{
38    const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = &[IsaExtension::new("zba", 1, 0)];
39
40    const ALIGNMENT: u8 = align_of::<u32>() as u8;
41
42    type Hart = Hart;
43
44    #[inline(always)]
45    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
46    fn try_decode(instruction: u32) -> Option<Self> {
47        let opcode = (instruction & 0b111_1111) as u8;
48        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
49        let funct3 = ((instruction >> 12) & 0b111) as u8;
50        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
51        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
52        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
53        let funct6 = ((instruction >> 26) & 0b11_1111) as u8;
54
55        match opcode {
56            // R-type
57            0b011_0011 => {
58                let rd = Reg::from_bits(rd_bits)?;
59                let rs1 = Reg::from_bits(rs1_bits)?;
60                let rs2 = Reg::from_bits(rs2_bits)?;
61                match (funct3, funct7) {
62                    (0b010, 0b001_0000) => Some(Self::Sh1add { rd, rs1, rs2 }),
63                    (0b100, 0b001_0000) => Some(Self::Sh2add { rd, rs1, rs2 }),
64                    (0b110, 0b001_0000) => Some(Self::Sh3add { rd, rs1, rs2 }),
65                    _ => None,
66                }
67            }
68            // I-type W (OP-IMM-32)
69            0b001_1011 => {
70                let rd = Reg::from_bits(rd_bits)?;
71                let rs1 = Reg::from_bits(rs1_bits)?;
72                // shamt is 6 bits: [25:20]
73                let shamt = Shamt::<u64>::new(((instruction >> 20) & 0x3f) as u8)?;
74                match (funct3, funct6) {
75                    (0b001, 0b00_0010) => Some(Self::SlliUw { rd, rs1, shamt }),
76                    _ => None,
77                }
78            }
79            // R-type W (OP-32)
80            0b011_1011 => {
81                let rd = Reg::from_bits(rd_bits)?;
82                let rs1 = Reg::from_bits(rs1_bits)?;
83                match funct3 {
84                    0b000 => {
85                        let rs2 = Reg::from_bits(rs2_bits)?;
86                        match funct7 {
87                            0b000_0100 => Some(Self::AddUw { rd, rs1, rs2 }),
88                            _ => None,
89                        }
90                    }
91                    0b010 => {
92                        let rs2 = Reg::from_bits(rs2_bits)?;
93                        match funct7 {
94                            0b001_0000 => Some(Self::Sh1addUw { rd, rs1, rs2 }),
95                            _ => None,
96                        }
97                    }
98                    0b100 => {
99                        let rs2 = Reg::from_bits(rs2_bits)?;
100                        match funct7 {
101                            0b001_0000 => Some(Self::Sh2addUw { rd, rs1, rs2 }),
102                            _ => None,
103                        }
104                    }
105                    0b110 => {
106                        let rs2 = Reg::from_bits(rs2_bits)?;
107                        match funct7 {
108                            0b001_0000 => Some(Self::Sh3addUw { rd, rs1, rs2 }),
109                            _ => None,
110                        }
111                    }
112                    _ => None,
113                }
114            }
115            _ => None,
116        }
117    }
118
119    #[inline(always)]
120    fn size(&self) -> u8 {
121        size_of::<u32>() as u8
122    }
123}
124
125#[instruction]
126impl<Reg, Hart> fmt::Display for Rv64ZbaInstruction<Hart>
127where
128    Reg: fmt::Display,
129    Hart: HartConfig<Reg = Reg>,
130{
131    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
132        match self {
133            Self::AddUw { rd, rs1, rs2 } => write!(f, "add.uw {rd}, {rs1}, {rs2}"),
134            Self::Sh1add { rd, rs1, rs2 } => write!(f, "sh1add {rd}, {rs1}, {rs2}"),
135            Self::Sh1addUw { rd, rs1, rs2 } => write!(f, "sh1add.uw {rd}, {rs1}, {rs2}"),
136            Self::Sh2add { rd, rs1, rs2 } => write!(f, "sh2add {rd}, {rs1}, {rs2}"),
137            Self::Sh2addUw { rd, rs1, rs2 } => write!(f, "sh2add.uw {rd}, {rs1}, {rs2}"),
138            Self::Sh3add { rd, rs1, rs2 } => write!(f, "sh3add {rd}, {rs1}, {rs2}"),
139            Self::Sh3addUw { rd, rs1, rs2 } => write!(f, "sh3add.uw {rd}, {rs1}, {rs2}"),
140            Self::SlliUw { rd, rs1, shamt } => write!(f, "slli.uw {rd}, {rs1}, {shamt}"),
141        }
142    }
143}
ab_riscv_primitives/instructions/rv64/b/zba.rs

ab_riscv_primitives/instructions/rv64/b/
zba.rs
