ab_riscv_primitives/instructions/rv64/
b.rs

1//! RV64 B extension
2
3pub mod zba;
4pub mod zbb;
5pub mod zbc;
6pub mod zbs;
7
8use crate::instructions::Instruction;
9use crate::instructions::rv64::b::zba::Rv64ZbaInstruction;
10use crate::instructions::rv64::b::zbb::Rv64ZbbInstruction;
11use crate::instructions::rv64::b::zbs::Rv64ZbsInstruction;
12use crate::registers::general_purpose::Register;
13use ab_riscv_macros::instruction;
14use core::fmt;
15
16/// RISC-V RV64 B (Zba + Zbb + Zbs) instruction
17#[instruction(
18    inherit = [Rv64ZbaInstruction, Rv64ZbbInstruction, Rv64ZbsInstruction]
19)]
20#[derive(Debug, Clone, Copy)]
21#[derive_const(PartialEq, Eq)]
22pub enum Rv64BInstruction<Reg> {}
23
24#[instruction]
25const impl<Reg> Instruction for Rv64BInstruction<Reg>
26where
27    Reg: [const] Register<Type = u64>,
28{
29    const ALIGNMENT: u8 = align_of::<u32>() as u8;
30
31    type Reg = Reg;
32
33    #[inline(always)]
34    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
35    fn try_decode(instruction: u32) -> Option<Self> {
36        None
37    }
38
39    #[inline(always)]
40    fn size(&self) -> u8 {
41        size_of::<u32>() as u8
42    }
43}
44
45#[instruction]
46impl<Reg> fmt::Display for Rv64BInstruction<Reg>
47where
48    Reg: fmt::Display + Copy,
49{
50    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
51        match self {}
52    }
53}
ab_riscv_primitives/instructions/rv64/b.rs

ab_riscv_primitives/instructions/rv64/
b.rs
