ab_riscv_primitives/instructions/rv64/a/
zalrsc.rs

1//! RV64 Zalrsc extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::hart::HartConfig;
7use crate::instructions::{ImplementedExtension, Instruction, IsaExtension};
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12/// RISC-V RV64 Zalrsc instruction (Load-Reserved/Store-Conditional)
13#[instruction]
14#[derive(Debug, Clone, Copy)]
15#[derive_const(PartialEq, Eq)]
16#[rustfmt::skip]
17pub enum Rv64ZalrscInstruction<Hart>
18where
19    Hart: HartConfig,
20{
21    Lr { rd: Hart::Reg, rs1: Hart::Reg, aq: bool, rl: bool },
22    Sc { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg, aq: bool, rl: bool },
23
24    LrD { rd: Hart::Reg, rs1: Hart::Reg, aq: bool, rl: bool },
25    ScD { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg, aq: bool, rl: bool },
26}
27
28#[instruction]
29const impl<Reg, Hart> Instruction for Rv64ZalrscInstruction<Hart>
30where
31    Reg: [const] Register<Type = u64>,
32    Hart: [const] HartConfig<Reg = Reg>,
33{
34    const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = &[IsaExtension::new("zalrsc", 1, 0)];
35
36    const ALIGNMENT: u8 = align_of::<u32>() as u8;
37
38    type Hart = Hart;
39
40    #[inline(always)]
41    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
42    fn try_decode(instruction: u32) -> Option<Self> {
43        let opcode = (instruction & 0b111_1111) as u8;
44        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
45        let funct3 = ((instruction >> 12) & 0b111) as u8;
46        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
47        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
48        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
49
50        match (opcode, funct3) {
51            // AMO, word- or doubleword-sized (the only sizes that exist in RV64)
52            (0b010_1111, 0b010 | 0b011) => {
53                let rd = Reg::from_bits(rd_bits)?;
54                let rs1 = Reg::from_bits(rs1_bits)?;
55                let funct5 = funct7 >> 2;
56                let aq = (funct7 & 0b10) != 0;
57                let rl = (funct7 & 0b01) != 0;
58
59                if funct3 == 0b010 {
60                    match (funct5, rs2_bits) {
61                        (0b00010, 0) => Some(Self::Lr { rd, rs1, aq, rl }),
62                        (0b00011, _) => {
63                            let rs2 = Reg::from_bits(rs2_bits)?;
64                            Some(Self::Sc {
65                                rd,
66                                rs1,
67                                rs2,
68                                aq,
69                                rl,
70                            })
71                        }
72                        _ => None,
73                    }
74                } else {
75                    match (funct5, rs2_bits) {
76                        (0b00010, 0) => Some(Self::LrD { rd, rs1, aq, rl }),
77                        (0b00011, _) => {
78                            let rs2 = Reg::from_bits(rs2_bits)?;
79                            Some(Self::ScD {
80                                rd,
81                                rs1,
82                                rs2,
83                                aq,
84                                rl,
85                            })
86                        }
87                        _ => None,
88                    }
89                }
90            }
91            _ => None,
92        }
93    }
94
95    #[inline(always)]
96    fn size(&self) -> u8 {
97        size_of::<u32>() as u8
98    }
99}
100
101/// Format `aq`/`rl` suffix for display
102#[inline(always)]
103fn aq_rl_suffix(aq: &bool, rl: &bool) -> &'static str {
104    match (*aq, *rl) {
105        (false, false) => "",
106        (true, false) => ".aq",
107        (false, true) => ".rl",
108        (true, true) => ".aqrl",
109    }
110}
111
112#[instruction]
113impl<Reg, Hart> fmt::Display for Rv64ZalrscInstruction<Hart>
114where
115    Reg: fmt::Display,
116    Hart: HartConfig<Reg = Reg>,
117{
118    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
119        #[rustfmt::skip]
120        match self {
121            Self::Lr { rd, rs1, aq, rl } => write!(f, "lr.w{} {rd}, ({rs1})", aq_rl_suffix(aq, rl)),
122            Self::Sc { rd, rs1, rs2, aq, rl } => write!(f, "sc.w{} {rd}, {rs2}, ({rs1})", aq_rl_suffix(aq, rl)),
123            Self::LrD { rd, rs1, aq, rl } => write!(f, "lr.d{} {rd}, ({rs1})", aq_rl_suffix(aq, rl)),
124            Self::ScD { rd, rs1, rs2, aq, rl } => write!(f, "sc.d{} {rd}, {rs2}, ({rs1})", aq_rl_suffix(aq, rl)),
125        }
126    }
127}
ab_riscv_primitives/instructions/rv64/a/zalrsc.rs

ab_riscv_primitives/instructions/rv64/a/
zalrsc.rs
