ab_riscv_primitives/instructions/rv64/a/
zalrsc.rs

1//! RV64 Zalrsc extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11/// RISC-V RV64 Zalrsc instruction (Load-Reserved/Store-Conditional)
12#[instruction]
13#[derive(Debug, Clone, Copy)]
14#[derive_const(PartialEq, Eq)]
15#[rustfmt::skip]
16pub enum Rv64ZalrscInstruction<Reg> {
17    Lr { rd: Reg, rs1: Reg, aq: bool, rl: bool },
18    Sc { rd: Reg, rs1: Reg, rs2: Reg, aq: bool, rl: bool },
19
20    LrD { rd: Reg, rs1: Reg, aq: bool, rl: bool },
21    ScD { rd: Reg, rs1: Reg, rs2: Reg, aq: bool, rl: bool },
22}
23
24#[instruction]
25const impl<Reg> Instruction for Rv64ZalrscInstruction<Reg>
26where
27    Reg: [const] Register<Type = u64>,
28{
29    const ALIGNMENT: u8 = align_of::<u32>() as u8;
30
31    type Reg = Reg;
32
33    #[inline(always)]
34    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
35    fn try_decode(instruction: u32) -> Option<Self> {
36        let opcode = (instruction & 0b111_1111) as u8;
37        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
38        let funct3 = ((instruction >> 12) & 0b111) as u8;
39        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
40        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
41        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
42
43        match (opcode, funct3) {
44            // AMO, word- or doubleword-sized (the only sizes that exist in RV64)
45            (0b010_1111, 0b010 | 0b011) => {
46                let rd = Reg::from_bits(rd_bits)?;
47                let rs1 = Reg::from_bits(rs1_bits)?;
48                let funct5 = funct7 >> 2;
49                let aq = (funct7 & 0b10) != 0;
50                let rl = (funct7 & 0b01) != 0;
51
52                if funct3 == 0b010 {
53                    match (funct5, rs2_bits) {
54                        (0b00010, 0) => Some(Self::Lr { rd, rs1, aq, rl }),
55                        (0b00011, _) => {
56                            let rs2 = Reg::from_bits(rs2_bits)?;
57                            Some(Self::Sc {
58                                rd,
59                                rs1,
60                                rs2,
61                                aq,
62                                rl,
63                            })
64                        }
65                        _ => None,
66                    }
67                } else {
68                    match (funct5, rs2_bits) {
69                        (0b00010, 0) => Some(Self::LrD { rd, rs1, aq, rl }),
70                        (0b00011, _) => {
71                            let rs2 = Reg::from_bits(rs2_bits)?;
72                            Some(Self::ScD {
73                                rd,
74                                rs1,
75                                rs2,
76                                aq,
77                                rl,
78                            })
79                        }
80                        _ => None,
81                    }
82                }
83            }
84            _ => None,
85        }
86    }
87
88    #[inline(always)]
89    fn size(&self) -> u8 {
90        size_of::<u32>() as u8
91    }
92}
93
94/// Format `aq`/`rl` suffix for display
95#[inline(always)]
96fn aq_rl_suffix(aq: &bool, rl: &bool) -> &'static str {
97    match (*aq, *rl) {
98        (false, false) => "",
99        (true, false) => ".aq",
100        (false, true) => ".rl",
101        (true, true) => ".aqrl",
102    }
103}
104
105#[instruction]
106impl<Reg> fmt::Display for Rv64ZalrscInstruction<Reg>
107where
108    Reg: fmt::Display,
109{
110    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
111        #[rustfmt::skip]
112        match self {
113            Self::Lr { rd, rs1, aq, rl } => write!(f, "lr.w{} {rd}, ({rs1})", aq_rl_suffix(aq, rl)),
114            Self::Sc { rd, rs1, rs2, aq, rl } => write!(f, "sc.w{} {rd}, {rs2}, ({rs1})", aq_rl_suffix(aq, rl)),
115            Self::LrD { rd, rs1, aq, rl } => write!(f, "lr.d{} {rd}, ({rs1})", aq_rl_suffix(aq, rl)),
116            Self::ScD { rd, rs1, rs2, aq, rl } => write!(f, "sc.d{} {rd}, {rs2}, ({rs1})", aq_rl_suffix(aq, rl)),
117        }
118    }
119}
ab_riscv_primitives/instructions/rv64/a/zalrsc.rs

ab_riscv_primitives/instructions/rv64/a/
zalrsc.rs
