ab_riscv_primitives/instructions/rv64/a/
zalrsc.rs

1//! RV64 Zalrsc extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11/// RISC-V RV64 Zalrsc instruction (Load-Reserved/Store-Conditional)
12#[instruction]
13#[derive(Debug, Clone, Copy)]
14#[derive_const(PartialEq, Eq)]
15#[rustfmt::skip]
16pub enum Rv64ZalrscInstruction<Reg> {
17    Lr { rd: Reg, rs1: Reg, aq: bool, rl: bool },
18    Sc { rd: Reg, rs1: Reg, rs2: Reg, aq: bool, rl: bool },
19
20    LrD { rd: Reg, rs1: Reg, aq: bool, rl: bool },
21    ScD { rd: Reg, rs1: Reg, rs2: Reg, aq: bool, rl: bool },
22}
23
24#[instruction]
25const impl<Reg> Instruction for Rv64ZalrscInstruction<Reg>
26where
27    Reg: [const] Register<Type = u64>,
28{
29    type Reg = Reg;
30
31    #[inline(always)]
32    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
33    fn try_decode(instruction: u32) -> Option<Self> {
34        let opcode = (instruction & 0b111_1111) as u8;
35        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
36        let funct3 = ((instruction >> 12) & 0b111) as u8;
37        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
38        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
39        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
40
41        match (opcode, funct3) {
42            // AMO, word- or doubleword-sized (the only sizes that exist in RV64)
43            (0b010_1111, 0b010 | 0b011) => {
44                let rd = Reg::from_bits(rd_bits)?;
45                let rs1 = Reg::from_bits(rs1_bits)?;
46                let funct5 = funct7 >> 2;
47                let aq = (funct7 & 0b10) != 0;
48                let rl = (funct7 & 0b01) != 0;
49
50                if funct3 == 0b010 {
51                    match (funct5, rs2_bits) {
52                        (0b00010, 0) => Some(Self::Lr { rd, rs1, aq, rl }),
53                        (0b00011, _) => {
54                            let rs2 = Reg::from_bits(rs2_bits)?;
55                            Some(Self::Sc {
56                                rd,
57                                rs1,
58                                rs2,
59                                aq,
60                                rl,
61                            })
62                        }
63                        _ => None,
64                    }
65                } else {
66                    match (funct5, rs2_bits) {
67                        (0b00010, 0) => Some(Self::LrD { rd, rs1, aq, rl }),
68                        (0b00011, _) => {
69                            let rs2 = Reg::from_bits(rs2_bits)?;
70                            Some(Self::ScD {
71                                rd,
72                                rs1,
73                                rs2,
74                                aq,
75                                rl,
76                            })
77                        }
78                        _ => None,
79                    }
80                }
81            }
82            _ => None,
83        }
84    }
85
86    #[inline(always)]
87    fn alignment() -> u8 {
88        align_of::<u32>() as u8
89    }
90
91    #[inline(always)]
92    fn size(&self) -> u8 {
93        size_of::<u32>() as u8
94    }
95}
96
97/// Format `aq`/`rl` suffix for display
98#[inline(always)]
99fn aq_rl_suffix(aq: &bool, rl: &bool) -> &'static str {
100    match (*aq, *rl) {
101        (false, false) => "",
102        (true, false) => ".aq",
103        (false, true) => ".rl",
104        (true, true) => ".aqrl",
105    }
106}
107
108#[instruction]
109impl<Reg> fmt::Display for Rv64ZalrscInstruction<Reg>
110where
111    Reg: fmt::Display,
112{
113    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
114        #[rustfmt::skip]
115        match self {
116            Self::Lr { rd, rs1, aq, rl } => write!(f, "lr.w{} {rd}, ({rs1})", aq_rl_suffix(aq, rl)),
117            Self::Sc { rd, rs1, rs2, aq, rl } => write!(f, "sc.w{} {rd}, {rs2}, ({rs1})", aq_rl_suffix(aq, rl)),
118            Self::LrD { rd, rs1, aq, rl } => write!(f, "lr.d{} {rd}, ({rs1})", aq_rl_suffix(aq, rl)),
119            Self::ScD { rd, rs1, rs2, aq, rl } => write!(f, "sc.d{} {rd}, {rs2}, ({rs1})", aq_rl_suffix(aq, rl)),
120        }
121    }
122}
ab_riscv_primitives/instructions/rv64/a/zalrsc.rs

ab_riscv_primitives/instructions/rv64/a/
zalrsc.rs
