ab_riscv_primitives/instructions/rv64/
a.rs

1//! RV64 A extension
2
3pub mod zaamo;
4pub mod zalrsc;
5
6use crate::instructions::Instruction;
7use crate::instructions::rv64::a::zaamo::Rv64ZaamoInstruction;
8use crate::instructions::rv64::a::zalrsc::Rv64ZalrscInstruction;
9use crate::registers::general_purpose::Register;
10use ab_riscv_macros::instruction;
11use core::fmt;
12
13/// RISC-V RV64 A (Zaamo + Zalrsc) instruction
14#[instruction(
15    inherit = [Rv64ZaamoInstruction, Rv64ZalrscInstruction]
16)]
17#[derive(Debug, Clone, Copy)]
18#[derive_const(PartialEq, Eq)]
19pub enum Rv64AInstruction<Reg> {}
20
21#[instruction]
22const impl<Reg> Instruction for Rv64AInstruction<Reg>
23where
24    Reg: [const] Register<Type = u64>,
25{
26    const ALIGNMENT: u8 = align_of::<u32>() as u8;
27
28    type Reg = Reg;
29
30    #[inline(always)]
31    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
32    fn try_decode(instruction: u32) -> Option<Self> {
33        None
34    }
35
36    #[inline(always)]
37    fn size(&self) -> u8 {
38        size_of::<u32>() as u8
39    }
40}
41
42#[instruction]
43impl<Reg> fmt::Display for Rv64AInstruction<Reg>
44where
45    Reg: fmt::Display + Copy,
46{
47    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
48        match self {}
49    }
50}
ab_riscv_primitives/instructions/rv64/a.rs

ab_riscv_primitives/instructions/rv64/
a.rs
