ab_riscv_primitives/instructions/

rv64.rs

//! Base RISC-V RV64 instruction set

pub mod a;
pub mod b;
pub mod c;
pub mod m;
#[cfg(test)]
mod tests;
pub mod zabha;
pub mod zacas;
pub mod zalasr;
pub mod zce;
pub mod zk;

use crate::hart::HartConfig;
use crate::instructions::utils::{I24, I24WithZeroedBits, Shamt};
use crate::instructions::{ImplementedExtension, Instruction, IsaExtension};
use crate::registers::general_purpose::Register;
use ab_riscv_macros::instruction;
use core::fmt;

/// RISC-V RV64 instruction
#[instruction]
#[derive(Debug, Clone, Copy)]
#[derive_const(PartialEq, Eq)]
#[rustfmt::skip]
pub enum Rv64Instruction<Hart>
where
    Hart: HartConfig,
{
    // R-type
    Add { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
    Sub { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
    Sll { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
    Slt { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
    Sltu { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
    Xor { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
    Srl { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
    Sra { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
    Or { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
    And { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },

    // RV64 R-type W
    Addw { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
    Subw { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
    Sllw { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
    Srlw { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
    Sraw { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },

    // I-type
    Addi { rd: Hart::Reg, rs1: Hart::Reg, imm: i16 },
    Slti { rd: Hart::Reg, rs1: Hart::Reg, imm: i16 },
    Sltiu { rd: Hart::Reg, rs1: Hart::Reg, imm: i16 },
    Xori { rd: Hart::Reg, rs1: Hart::Reg, imm: i16 },
    Ori { rd: Hart::Reg, rs1: Hart::Reg, imm: i16 },
    Andi { rd: Hart::Reg, rs1: Hart::Reg, imm: i16 },
    Slli { rd: Hart::Reg, rs1: Hart::Reg, shamt: Shamt<u64> },
    Srli { rd: Hart::Reg, rs1: Hart::Reg, shamt: Shamt<u64> },
    Srai { rd: Hart::Reg, rs1: Hart::Reg, shamt: Shamt<u64> },

    // RV64 I-type W
    Addiw { rd: Hart::Reg, rs1: Hart::Reg, imm: i16 },
    Slliw { rd: Hart::Reg, rs1: Hart::Reg, shamt: Shamt<u32> },
    Srliw { rd: Hart::Reg, rs1: Hart::Reg, shamt: Shamt<u32> },
    Sraiw { rd: Hart::Reg, rs1: Hart::Reg, shamt: Shamt<u32> },

    // Loads (I-type)
    Lb { rd: Hart::Reg, rs1: Hart::Reg, imm: i16 },
    Lh { rd: Hart::Reg, rs1: Hart::Reg, imm: i16 },
    Lw { rd: Hart::Reg, rs1: Hart::Reg, imm: i16 },
    Ld { rd: Hart::Reg, rs1: Hart::Reg, imm: i16 },
    Lbu { rd: Hart::Reg, rs1: Hart::Reg, imm: i16 },
    Lhu { rd: Hart::Reg, rs1: Hart::Reg, imm: i16 },
    Lwu { rd: Hart::Reg, rs1: Hart::Reg, imm: i16 },

    // Jalr (I-type)
    Jalr { rd: Hart::Reg, rs1: Hart::Reg, imm: i16 },

    // S-type
    Sb { rs2: Hart::Reg, rs1: Hart::Reg, imm: i16 },
    Sh { rs2: Hart::Reg, rs1: Hart::Reg, imm: i16 },
    Sw { rs2: Hart::Reg, rs1: Hart::Reg, imm: i16 },
    Sd { rs2: Hart::Reg, rs1: Hart::Reg, imm: i16 },

    // B-type
    Beq { rs1: Hart::Reg, rs2: Hart::Reg, imm: i16 },
    Bne { rs1: Hart::Reg, rs2: Hart::Reg, imm: i16 },
    Blt { rs1: Hart::Reg, rs2: Hart::Reg, imm: i16 },
    Bge { rs1: Hart::Reg, rs2: Hart::Reg, imm: i16 },
    Bltu { rs1: Hart::Reg, rs2: Hart::Reg, imm: i16 },
    Bgeu { rs1: Hart::Reg, rs2: Hart::Reg, imm: i16 },

    // Lui (U-type)
    Lui { rd: Hart::Reg, imm: I24WithZeroedBits<12> },

    // Auipc (U-type)
    Auipc { rd: Hart::Reg, imm: I24WithZeroedBits<12> },

    // Jal (J-type)
    Jal { rd: Hart::Reg, imm: I24 },

    // Fence
    Fence { pred: u8, succ: u8 },
    FenceTso,

    // System instructions
    Ecall,
    Ebreak,

    // Unimplemented/illegal
    Unimp,
}

#[instruction]
const impl<Reg, Hart> Instruction for Rv64Instruction<Hart>
where
    Reg: [const] Register<Type = u64>,
    Hart: [const] HartConfig<Reg = Reg>,
{
    const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = if Reg::RVE {
        &[IsaExtension::new("e", 2, 0)]
    } else {
        &[IsaExtension::new("i", 2, 1)]
    };

    const ALIGNMENT: u8 = align_of::<u32>() as u8;

    type Hart = Hart;

    #[inline(always)]
    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
    fn try_decode(instruction: u32) -> Option<Self> {
        let opcode = (instruction & 0b111_1111) as u8;
        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
        let funct3 = ((instruction >> 12) & 0b111) as u8;
        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;

        match opcode {
            // R-type
            0b011_0011 => {
                let rd = Reg::from_bits(rd_bits)?;
                let rs1 = Reg::from_bits(rs1_bits)?;
                let rs2 = Reg::from_bits(rs2_bits)?;
                match (funct3, funct7) {
                    (0b000, 0b000_0000) => Some(Self::Add { rd, rs1, rs2 }),
                    (0b000, 0b010_0000) => Some(Self::Sub { rd, rs1, rs2 }),
                    (0b001, 0b000_0000) => Some(Self::Sll { rd, rs1, rs2 }),
                    (0b010, 0b000_0000) => Some(Self::Slt { rd, rs1, rs2 }),
                    (0b011, 0b000_0000) => Some(Self::Sltu { rd, rs1, rs2 }),
                    (0b100, 0b000_0000) => Some(Self::Xor { rd, rs1, rs2 }),
                    (0b101, 0b000_0000) => Some(Self::Srl { rd, rs1, rs2 }),
                    (0b101, 0b010_0000) => Some(Self::Sra { rd, rs1, rs2 }),
                    (0b110, 0b000_0000) => Some(Self::Or { rd, rs1, rs2 }),
                    (0b111, 0b000_0000) => Some(Self::And { rd, rs1, rs2 }),
                    _ => None,
                }
            }
            // RV64 R-type W
            0b011_1011 => {
                let rd = Reg::from_bits(rd_bits)?;
                let rs1 = Reg::from_bits(rs1_bits)?;
                let rs2 = Reg::from_bits(rs2_bits)?;
                match (funct3, funct7) {
                    (0b000, 0b000_0000) => Some(Self::Addw { rd, rs1, rs2 }),
                    (0b000, 0b010_0000) => Some(Self::Subw { rd, rs1, rs2 }),
                    (0b001, 0b000_0000) => Some(Self::Sllw { rd, rs1, rs2 }),
                    (0b101, 0b000_0000) => Some(Self::Srlw { rd, rs1, rs2 }),
                    (0b101, 0b010_0000) => Some(Self::Sraw { rd, rs1, rs2 }),
                    _ => None,
                }
            }
            // I-type
            0b001_0011 => {
                let rd = Reg::from_bits(rd_bits)?;
                let rs1 = Reg::from_bits(rs1_bits)?;
                let imm = (instruction.cast_signed() >> 20) as i16;
                match funct3 {
                    0b000 => Some(Self::Addi { rd, rs1, imm }),
                    0b010 => Some(Self::Slti { rd, rs1, imm }),
                    0b011 => Some(Self::Sltiu { rd, rs1, imm }),
                    0b100 => Some(Self::Xori { rd, rs1, imm }),
                    0b110 => Some(Self::Ori { rd, rs1, imm }),
                    0b111 => Some(Self::Andi { rd, rs1, imm }),
                    0b001 => {
                        let shamt = Shamt::<u64>::new((instruction >> 20) as u8 & 0b11_1111)?;
                        let funct6 = (instruction >> 26) & 0b11_1111;
                        if funct6 == 0b00_0000 {
                            Some(Self::Slli { rd, rs1, shamt })
                        } else {
                            None
                        }
                    }
                    0b101 => {
                        let shamt = Shamt::<u64>::new((instruction >> 20) as u8 & 0b11_1111)?;
                        let funct6 = (instruction >> 26) & 0b11_1111;
                        match funct6 {
                            0b00_0000 => Some(Self::Srli { rd, rs1, shamt }),
                            0b01_0000 => Some(Self::Srai { rd, rs1, shamt }),
                            _ => None,
                        }
                    }
                    _ => None,
                }
            }
            // RV64 I-type W
            0b001_1011 => {
                let rd = Reg::from_bits(rd_bits)?;
                let rs1 = Reg::from_bits(rs1_bits)?;
                let imm = (instruction.cast_signed() >> 20) as i16;
                // 5-bit for W shifts
                let shamt = Shamt::<u32>::new((instruction >> 20) as u8 & 0b1_1111)?;
                match funct3 {
                    0b000 => Some(Self::Addiw { rd, rs1, imm }),
                    0b001 => {
                        if funct7 == 0b000_0000 {
                            Some(Self::Slliw { rd, rs1, shamt })
                        } else {
                            None
                        }
                    }
                    0b101 => match funct7 {
                        0b000_0000 => Some(Self::Srliw { rd, rs1, shamt }),
                        0b010_0000 => Some(Self::Sraiw { rd, rs1, shamt }),
                        _ => None,
                    },
                    _ => None,
                }
            }
            // Loads (I-type)
            0b000_0011 => {
                let rd = Reg::from_bits(rd_bits)?;
                let rs1 = Reg::from_bits(rs1_bits)?;
                let imm = (instruction.cast_signed() >> 20) as i16;
                match funct3 {
                    0b000 => Some(Self::Lb { rd, rs1, imm }),
                    0b001 => Some(Self::Lh { rd, rs1, imm }),
                    0b010 => Some(Self::Lw { rd, rs1, imm }),
                    0b011 => Some(Self::Ld { rd, rs1, imm }),
                    0b100 => Some(Self::Lbu { rd, rs1, imm }),
                    0b101 => Some(Self::Lhu { rd, rs1, imm }),
                    0b110 => Some(Self::Lwu { rd, rs1, imm }),
                    _ => None,
                }
            }
            // Jalr (I-type)
            0b110_0111 => {
                let rd = Reg::from_bits(rd_bits)?;
                let rs1 = Reg::from_bits(rs1_bits)?;
                if funct3 == 0b000 {
                    let imm = (instruction.cast_signed() >> 20) as i16;
                    Some(Self::Jalr { rd, rs1, imm })
                } else {
                    None
                }
            }
            // S-type
            0b010_0011 => {
                let rs1 = Reg::from_bits(rs1_bits)?;
                let rs2 = Reg::from_bits(rs2_bits)?;
                let imm11_5 = ((instruction >> 25) & 0b111_1111).cast_signed();
                let imm4_0 = ((instruction >> 7) & 0b1_1111).cast_signed();
                let imm = (imm11_5 << 5) | imm4_0;
                // Sign extend
                let imm = ((imm << 20) >> 20) as i16;
                match funct3 {
                    0b000 => Some(Self::Sb { rs2, rs1, imm }),
                    0b001 => Some(Self::Sh { rs2, rs1, imm }),
                    0b010 => Some(Self::Sw { rs2, rs1, imm }),
                    0b011 => Some(Self::Sd { rs2, rs1, imm }),
                    _ => None,
                }
            }
            // B-type
            0b110_0011 => {
                let rs1 = Reg::from_bits(rs1_bits)?;
                let rs2 = Reg::from_bits(rs2_bits)?;
                let imm12 = ((instruction >> 31) & 1).cast_signed();
                let imm10_5 = ((instruction >> 25) & 0b11_1111).cast_signed();
                let imm4_1 = ((instruction >> 8) & 0b1111).cast_signed();
                let imm11 = ((instruction >> 7) & 1).cast_signed();
                let imm = (imm12 << 12) | (imm11 << 11) | (imm10_5 << 5) | (imm4_1 << 1);
                // Sign extend
                let imm = ((imm << 19) >> 19) as i16;
                match funct3 {
                    0b000 => Some(Self::Beq { rs1, rs2, imm }),
                    0b001 => Some(Self::Bne { rs1, rs2, imm }),
                    0b100 => Some(Self::Blt { rs1, rs2, imm }),
                    0b101 => Some(Self::Bge { rs1, rs2, imm }),
                    0b110 => Some(Self::Bltu { rs1, rs2, imm }),
                    0b111 => Some(Self::Bgeu { rs1, rs2, imm }),
                    _ => None,
                }
            }
            // Lui (U-type)
            0b011_0111 => {
                let rd = Reg::from_bits(rd_bits)?;
                let imm = I24WithZeroedBits::from_i32((instruction & 0xffff_f000).cast_signed());
                Some(Self::Lui { rd, imm })
            }
            // Auipc (U-type)
            0b001_0111 => {
                let rd = Reg::from_bits(rd_bits)?;
                let imm = I24WithZeroedBits::from_i32((instruction & 0xffff_f000).cast_signed());
                Some(Self::Auipc { rd, imm })
            }
            // Jal (J-type)
            0b110_1111 => {
                let rd = Reg::from_bits(rd_bits)?;
                let imm20 = ((instruction >> 31) & 1).cast_signed();
                let imm10_1 = ((instruction >> 21) & 0b11_1111_1111).cast_signed();
                let imm11 = ((instruction >> 20) & 1).cast_signed();
                let imm19_12 = ((instruction >> 12) & 0b1111_1111).cast_signed();
                let imm = (imm20 << 20) | (imm19_12 << 12) | (imm11 << 11) | (imm10_1 << 1);
                // Sign extend
                let imm = I24::from_i32((imm << 11) >> 11);
                Some(Self::Jal { rd, imm })
            }
            // Fence (I-type like, simplified for EM)
            0b000_1111 => {
                if funct3 == 0b000 {
                    let fm = (instruction >> 28) & 0b1111;
                    let pred = ((instruction >> 24) & 0xf) as u8;
                    let succ = ((instruction >> 20) & 0xf) as u8;
                    if fm == 0b1000 && pred == 0b0011 && succ == 0b0011 {
                        // FENCE.TSO: fm=8, pred=RW(0b0011), succ=RW(0b0011) - fixed by spec
                        Some(Self::FenceTso)
                    } else {
                        // rd, rs1, and any other fm/pred/succ combination are reserved for
                        // finer-grain fences and hints; implementations that don't support those
                        // must ignore them and execute an ordinary (conservative) fence rather
                        // than trapping.
                        Some(Self::Fence { pred, succ })
                    }
                } else {
                    None
                }
            }
            // System instructions
            0b111_0011 => {
                let imm = (instruction >> 20) & 0xfff;
                if funct3 == 0 && rd_bits == 0 && rs1_bits == 0 {
                    match imm {
                        0 => Some(Self::Ecall),
                        1 => Some(Self::Ebreak),
                        _ => None,
                    }
                } else if funct3 == 0b001 && rd_bits == 0 && rs1_bits == 0 && imm == 0xc00 {
                    // `0xc000_1073` is emitted as `unimp`/illegal instruction by various compilers,
                    // including Rust when it hits a panic
                    Some(Self::Unimp)
                } else {
                    None
                }
            }
            _ => None,
        }
    }

    #[inline(always)]
    fn size(&self) -> u8 {
        size_of::<u32>() as u8
    }
}

#[instruction]
impl<Reg, Hart> fmt::Display for Rv64Instruction<Hart>
where
    Reg: fmt::Display,
    Hart: HartConfig<Reg = Reg>,
{
    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
        match self {
            Self::Add { rd, rs1, rs2 } => write!(f, "add {rd}, {rs1}, {rs2}"),
            Self::Sub { rd, rs1, rs2 } => write!(f, "sub {rd}, {rs1}, {rs2}"),
            Self::Sll { rd, rs1, rs2 } => write!(f, "sll {rd}, {rs1}, {rs2}"),
            Self::Slt { rd, rs1, rs2 } => write!(f, "slt {rd}, {rs1}, {rs2}"),
            Self::Sltu { rd, rs1, rs2 } => write!(f, "sltu {rd}, {rs1}, {rs2}"),
            Self::Xor { rd, rs1, rs2 } => write!(f, "xor {rd}, {rs1}, {rs2}"),
            Self::Srl { rd, rs1, rs2 } => write!(f, "srl {rd}, {rs1}, {rs2}"),
            Self::Sra { rd, rs1, rs2 } => write!(f, "sra {rd}, {rs1}, {rs2}"),
            Self::Or { rd, rs1, rs2 } => write!(f, "or {rd}, {rs1}, {rs2}"),
            Self::And { rd, rs1, rs2 } => write!(f, "and {rd}, {rs1}, {rs2}"),

            Self::Addw { rd, rs1, rs2 } => write!(f, "addw {rd}, {rs1}, {rs2}"),
            Self::Subw { rd, rs1, rs2 } => write!(f, "subw {rd}, {rs1}, {rs2}"),
            Self::Sllw { rd, rs1, rs2 } => write!(f, "sllw {rd}, {rs1}, {rs2}"),
            Self::Srlw { rd, rs1, rs2 } => write!(f, "srlw {rd}, {rs1}, {rs2}"),
            Self::Sraw { rd, rs1, rs2 } => write!(f, "sraw {rd}, {rs1}, {rs2}"),

            Self::Addi { rd, rs1, imm } => write!(f, "addi {rd}, {rs1}, {imm}"),
            Self::Slti { rd, rs1, imm } => write!(f, "slti {rd}, {rs1}, {imm}"),
            Self::Sltiu { rd, rs1, imm } => write!(f, "sltiu {rd}, {rs1}, {imm}"),
            Self::Xori { rd, rs1, imm } => write!(f, "xori {rd}, {rs1}, {imm}"),
            Self::Ori { rd, rs1, imm } => write!(f, "ori {rd}, {rs1}, {imm}"),
            Self::Andi { rd, rs1, imm } => write!(f, "andi {rd}, {rs1}, {imm}"),
            Self::Slli { rd, rs1, shamt } => write!(f, "slli {rd}, {rs1}, {shamt}"),
            Self::Srli { rd, rs1, shamt } => write!(f, "srli {rd}, {rs1}, {shamt}"),
            Self::Srai { rd, rs1, shamt } => write!(f, "srai {rd}, {rs1}, {shamt}"),

            Self::Addiw { rd, rs1, imm } => write!(f, "addiw {rd}, {rs1}, {imm}"),
            Self::Slliw { rd, rs1, shamt } => write!(f, "slliw {rd}, {rs1}, {shamt}"),
            Self::Srliw { rd, rs1, shamt } => write!(f, "srliw {rd}, {rs1}, {shamt}"),
            Self::Sraiw { rd, rs1, shamt } => write!(f, "sraiw {rd}, {rs1}, {shamt}"),

            Self::Lb { rd, rs1, imm } => write!(f, "lb {rd}, {imm}({rs1})"),
            Self::Lh { rd, rs1, imm } => write!(f, "lh {rd}, {imm}({rs1})"),
            Self::Lw { rd, rs1, imm } => write!(f, "lw {rd}, {imm}({rs1})"),
            Self::Ld { rd, rs1, imm } => write!(f, "ld {rd}, {imm}({rs1})"),
            Self::Lbu { rd, rs1, imm } => write!(f, "lbu {rd}, {imm}({rs1})"),
            Self::Lhu { rd, rs1, imm } => write!(f, "lhu {rd}, {imm}({rs1})"),
            Self::Lwu { rd, rs1, imm } => write!(f, "lwu {rd}, {imm}({rs1})"),

            Self::Jalr { rd, rs1, imm } => write!(f, "jalr {rd}, {imm}({rs1})"),

            Self::Sb { rs2, rs1, imm } => write!(f, "sb {rs2}, {imm}({rs1})"),
            Self::Sh { rs2, rs1, imm } => write!(f, "sh {rs2}, {imm}({rs1})"),
            Self::Sw { rs2, rs1, imm } => write!(f, "sw {rs2}, {imm}({rs1})"),
            Self::Sd { rs2, rs1, imm } => write!(f, "sd {rs2}, {imm}({rs1})"),

            Self::Beq { rs1, rs2, imm } => write!(f, "beq {rs1}, {rs2}, {imm}"),
            Self::Bne { rs1, rs2, imm } => write!(f, "bne {rs1}, {rs2}, {imm}"),
            Self::Blt { rs1, rs2, imm } => write!(f, "blt {rs1}, {rs2}, {imm}"),
            Self::Bge { rs1, rs2, imm } => write!(f, "bge {rs1}, {rs2}, {imm}"),
            Self::Bltu { rs1, rs2, imm } => write!(f, "bltu {rs1}, {rs2}, {imm}"),
            Self::Bgeu { rs1, rs2, imm } => write!(f, "bgeu {rs1}, {rs2}, {imm}"),

            Self::Lui { rd, imm } => write!(f, "lui {rd}, 0x{:x}", imm.to_i32() >> 12),

            Self::Auipc { rd, imm } => write!(f, "auipc {rd}, 0x{:x}", imm.to_i32() >> 12),

            Self::Jal { rd, imm } => write!(f, "jal {rd}, {imm}"),

            Self::Fence { pred, succ } => write!(f, "fence {pred}, {succ}"),
            Self::FenceTso => write!(f, "fence.tso"),

            Self::Ecall => write!(f, "ecall"),
            Self::Ebreak => write!(f, "ebreak"),

            Self::Unimp => write!(f, "unimp"),
        }
    }
}