ab_riscv_primitives/instructions/
rv64.rs

1//! Base RISC-V RV64 instruction set
2
3use crate::instructions::Instruction;
4use crate::registers::general_purpose::Register;
5use ab_riscv_macros::instruction;
6use core::fmt;
7
8pub mod b;
9pub mod m;
10#[cfg(test)]
11mod tests;
12pub mod v;
13pub mod zicsr;
14pub mod zk;
15
16/// RISC-V RV64 instruction
17#[instruction]
18#[derive(Debug, Clone, Copy, PartialEq, Eq)]
19pub enum Rv64Instruction<Reg> {
20    // R-type
21    Add { rd: Reg, rs1: Reg, rs2: Reg },
22    Sub { rd: Reg, rs1: Reg, rs2: Reg },
23    Sll { rd: Reg, rs1: Reg, rs2: Reg },
24    Slt { rd: Reg, rs1: Reg, rs2: Reg },
25    Sltu { rd: Reg, rs1: Reg, rs2: Reg },
26    Xor { rd: Reg, rs1: Reg, rs2: Reg },
27    Srl { rd: Reg, rs1: Reg, rs2: Reg },
28    Sra { rd: Reg, rs1: Reg, rs2: Reg },
29    Or { rd: Reg, rs1: Reg, rs2: Reg },
30    And { rd: Reg, rs1: Reg, rs2: Reg },
31
32    // RV64 R-type W
33    Addw { rd: Reg, rs1: Reg, rs2: Reg },
34    Subw { rd: Reg, rs1: Reg, rs2: Reg },
35    Sllw { rd: Reg, rs1: Reg, rs2: Reg },
36    Srlw { rd: Reg, rs1: Reg, rs2: Reg },
37    Sraw { rd: Reg, rs1: Reg, rs2: Reg },
38
39    // I-type
40    Addi { rd: Reg, rs1: Reg, imm: i16 },
41    Slti { rd: Reg, rs1: Reg, imm: i16 },
42    Sltiu { rd: Reg, rs1: Reg, imm: i16 },
43    Xori { rd: Reg, rs1: Reg, imm: i16 },
44    Ori { rd: Reg, rs1: Reg, imm: i16 },
45    Andi { rd: Reg, rs1: Reg, imm: i16 },
46    Slli { rd: Reg, rs1: Reg, shamt: u8 },
47    Srli { rd: Reg, rs1: Reg, shamt: u8 },
48    Srai { rd: Reg, rs1: Reg, shamt: u8 },
49
50    // RV64 I-type W
51    Addiw { rd: Reg, rs1: Reg, imm: i16 },
52    Slliw { rd: Reg, rs1: Reg, shamt: u8 },
53    Srliw { rd: Reg, rs1: Reg, shamt: u8 },
54    Sraiw { rd: Reg, rs1: Reg, shamt: u8 },
55
56    // Loads (I-type)
57    Lb { rd: Reg, rs1: Reg, imm: i16 },
58    Lh { rd: Reg, rs1: Reg, imm: i16 },
59    Lw { rd: Reg, rs1: Reg, imm: i16 },
60    Ld { rd: Reg, rs1: Reg, imm: i16 },
61    Lbu { rd: Reg, rs1: Reg, imm: i16 },
62    Lhu { rd: Reg, rs1: Reg, imm: i16 },
63    Lwu { rd: Reg, rs1: Reg, imm: i16 },
64
65    // Jalr (I-type)
66    Jalr { rd: Reg, rs1: Reg, imm: i16 },
67
68    // S-type
69    Sb { rs2: Reg, rs1: Reg, imm: i16 },
70    Sh { rs2: Reg, rs1: Reg, imm: i16 },
71    Sw { rs2: Reg, rs1: Reg, imm: i16 },
72    Sd { rs2: Reg, rs1: Reg, imm: i16 },
73
74    // B-type
75    Beq { rs1: Reg, rs2: Reg, imm: i32 },
76    Bne { rs1: Reg, rs2: Reg, imm: i32 },
77    Blt { rs1: Reg, rs2: Reg, imm: i32 },
78    Bge { rs1: Reg, rs2: Reg, imm: i32 },
79    Bltu { rs1: Reg, rs2: Reg, imm: i32 },
80    Bgeu { rs1: Reg, rs2: Reg, imm: i32 },
81
82    // Lui (U-type)
83    Lui { rd: Reg, imm: i32 },
84
85    // Auipc (U-type)
86    Auipc { rd: Reg, imm: i32 },
87
88    // Jal (J-type)
89    Jal { rd: Reg, imm: i32 },
90
91    // Fence
92    Fence { pred: u8, succ: u8 },
93
94    // System instructions
95    Ecall,
96    Ebreak,
97
98    // Unimplemented/illegal
99    Unimp,
100}
101
102#[instruction]
103impl<Reg> const Instruction for Rv64Instruction<Reg>
104where
105    Reg: [const] Register<Type = u64>,
106{
107    type Reg = Reg;
108
109    #[inline(always)]
110    fn try_decode(instruction: u32) -> Option<Self> {
111        let opcode = (instruction & 0b111_1111) as u8;
112        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
113        let funct3 = ((instruction >> 12) & 0b111) as u8;
114        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
115        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
116        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
117
118        match opcode {
119            // R-type
120            0b0110011 => {
121                let rd = Reg::from_bits(rd_bits)?;
122                let rs1 = Reg::from_bits(rs1_bits)?;
123                let rs2 = Reg::from_bits(rs2_bits)?;
124                match (funct3, funct7) {
125                    (0b000, 0b0000000) => Some(Self::Add { rd, rs1, rs2 }),
126                    (0b000, 0b0100000) => Some(Self::Sub { rd, rs1, rs2 }),
127                    (0b001, 0b0000000) => Some(Self::Sll { rd, rs1, rs2 }),
128                    (0b010, 0b0000000) => Some(Self::Slt { rd, rs1, rs2 }),
129                    (0b011, 0b0000000) => Some(Self::Sltu { rd, rs1, rs2 }),
130                    (0b100, 0b0000000) => Some(Self::Xor { rd, rs1, rs2 }),
131                    (0b101, 0b0000000) => Some(Self::Srl { rd, rs1, rs2 }),
132                    (0b101, 0b0100000) => Some(Self::Sra { rd, rs1, rs2 }),
133                    (0b110, 0b0000000) => Some(Self::Or { rd, rs1, rs2 }),
134                    (0b111, 0b0000000) => Some(Self::And { rd, rs1, rs2 }),
135                    _ => None,
136                }
137            }
138            // RV64 R-type W
139            0b0111011 => {
140                let rd = Reg::from_bits(rd_bits)?;
141                let rs1 = Reg::from_bits(rs1_bits)?;
142                let rs2 = Reg::from_bits(rs2_bits)?;
143                match (funct3, funct7) {
144                    (0b000, 0b0000000) => Some(Self::Addw { rd, rs1, rs2 }),
145                    (0b000, 0b0100000) => Some(Self::Subw { rd, rs1, rs2 }),
146                    (0b001, 0b0000000) => Some(Self::Sllw { rd, rs1, rs2 }),
147                    (0b101, 0b0000000) => Some(Self::Srlw { rd, rs1, rs2 }),
148                    (0b101, 0b0100000) => Some(Self::Sraw { rd, rs1, rs2 }),
149                    _ => None,
150                }
151            }
152            // I-type
153            0b0010011 => {
154                let rd = Reg::from_bits(rd_bits)?;
155                let rs1 = Reg::from_bits(rs1_bits)?;
156                let imm = (instruction.cast_signed() >> 20) as i16;
157                match funct3 {
158                    0b000 => Some(Self::Addi { rd, rs1, imm }),
159                    0b010 => Some(Self::Slti { rd, rs1, imm }),
160                    0b011 => Some(Self::Sltiu { rd, rs1, imm }),
161                    0b100 => Some(Self::Xori { rd, rs1, imm }),
162                    0b110 => Some(Self::Ori { rd, rs1, imm }),
163                    0b111 => Some(Self::Andi { rd, rs1, imm }),
164                    0b001 => {
165                        let shamt = (instruction >> 20) as u8 & 0b11_1111;
166                        let funct6 = (instruction >> 26) & 0b11_1111;
167                        if funct6 == 0b000000 {
168                            Some(Self::Slli { rd, rs1, shamt })
169                        } else {
170                            None
171                        }
172                    }
173                    0b101 => {
174                        let shamt = (instruction >> 20) as u8 & 0b11_1111;
175                        let funct6 = (instruction >> 26) & 0b11_1111;
176                        match funct6 {
177                            0b000000 => Some(Self::Srli { rd, rs1, shamt }),
178                            0b010000 => Some(Self::Srai { rd, rs1, shamt }),
179                            _ => None,
180                        }
181                    }
182                    _ => None,
183                }
184            }
185            // RV64 I-type W
186            0b0011011 => {
187                let rd = Reg::from_bits(rd_bits)?;
188                let rs1 = Reg::from_bits(rs1_bits)?;
189                let imm = (instruction.cast_signed() >> 20) as i16;
190                // 5-bit for W shifts
191                let shamt = (instruction >> 20) as u8 & 0b1_1111;
192                match funct3 {
193                    0b000 => Some(Self::Addiw { rd, rs1, imm }),
194                    0b001 => {
195                        if funct7 == 0b0000000 {
196                            Some(Self::Slliw { rd, rs1, shamt })
197                        } else {
198                            None
199                        }
200                    }
201                    0b101 => match funct7 {
202                        0b0000000 => Some(Self::Srliw { rd, rs1, shamt }),
203                        0b0100000 => Some(Self::Sraiw { rd, rs1, shamt }),
204                        _ => None,
205                    },
206                    _ => None,
207                }
208            }
209            // Loads (I-type)
210            0b0000011 => {
211                let rd = Reg::from_bits(rd_bits)?;
212                let rs1 = Reg::from_bits(rs1_bits)?;
213                let imm = (instruction.cast_signed() >> 20) as i16;
214                match funct3 {
215                    0b000 => Some(Self::Lb { rd, rs1, imm }),
216                    0b001 => Some(Self::Lh { rd, rs1, imm }),
217                    0b010 => Some(Self::Lw { rd, rs1, imm }),
218                    0b011 => Some(Self::Ld { rd, rs1, imm }),
219                    0b100 => Some(Self::Lbu { rd, rs1, imm }),
220                    0b101 => Some(Self::Lhu { rd, rs1, imm }),
221                    0b110 => Some(Self::Lwu { rd, rs1, imm }),
222                    _ => None,
223                }
224            }
225            // Jalr (I-type)
226            0b1100111 => {
227                let rd = Reg::from_bits(rd_bits)?;
228                let rs1 = Reg::from_bits(rs1_bits)?;
229                if funct3 == 0b000 {
230                    let imm = (instruction.cast_signed() >> 20) as i16;
231                    Some(Self::Jalr { rd, rs1, imm })
232                } else {
233                    None
234                }
235            }
236            // S-type
237            0b0100011 => {
238                let rs1 = Reg::from_bits(rs1_bits)?;
239                let rs2 = Reg::from_bits(rs2_bits)?;
240                let imm11_5 = ((instruction >> 25) & 0b111_1111).cast_signed();
241                let imm4_0 = ((instruction >> 7) & 0b1_1111).cast_signed();
242                let imm = (imm11_5 << 5) | imm4_0;
243                // Sign extend
244                let imm = ((imm << 20) >> 20) as i16;
245                match funct3 {
246                    0b000 => Some(Self::Sb { rs2, rs1, imm }),
247                    0b001 => Some(Self::Sh { rs2, rs1, imm }),
248                    0b010 => Some(Self::Sw { rs2, rs1, imm }),
249                    0b011 => Some(Self::Sd { rs2, rs1, imm }),
250                    _ => None,
251                }
252            }
253            // B-type
254            0b1100011 => {
255                let rs1 = Reg::from_bits(rs1_bits)?;
256                let rs2 = Reg::from_bits(rs2_bits)?;
257                let imm12 = ((instruction >> 31) & 1).cast_signed();
258                let imm10_5 = ((instruction >> 25) & 0b11_1111).cast_signed();
259                let imm4_1 = ((instruction >> 8) & 0b1111).cast_signed();
260                let imm11 = ((instruction >> 7) & 1).cast_signed();
261                let imm = (imm12 << 12) | (imm11 << 11) | (imm10_5 << 5) | (imm4_1 << 1);
262                // Sign extend
263                let imm = (imm << 19) >> 19;
264                match funct3 {
265                    0b000 => Some(Self::Beq { rs1, rs2, imm }),
266                    0b001 => Some(Self::Bne { rs1, rs2, imm }),
267                    0b100 => Some(Self::Blt { rs1, rs2, imm }),
268                    0b101 => Some(Self::Bge { rs1, rs2, imm }),
269                    0b110 => Some(Self::Bltu { rs1, rs2, imm }),
270                    0b111 => Some(Self::Bgeu { rs1, rs2, imm }),
271                    _ => None,
272                }
273            }
274            // Lui (U-type)
275            0b0110111 => {
276                let rd = Reg::from_bits(rd_bits)?;
277                let imm = (instruction & 0xffff_f000).cast_signed();
278                Some(Self::Lui { rd, imm })
279            }
280            // Auipc (U-type)
281            0b0010111 => {
282                let rd = Reg::from_bits(rd_bits)?;
283                let imm = (instruction & 0xffff_f000).cast_signed();
284                Some(Self::Auipc { rd, imm })
285            }
286            // Jal (J-type)
287            0b1101111 => {
288                let rd = Reg::from_bits(rd_bits)?;
289                let imm20 = ((instruction >> 31) & 1).cast_signed();
290                let imm10_1 = ((instruction >> 21) & 0b11_1111_1111).cast_signed();
291                let imm11 = ((instruction >> 20) & 1).cast_signed();
292                let imm19_12 = ((instruction >> 12) & 0b1111_1111).cast_signed();
293                let imm = (imm20 << 20) | (imm19_12 << 12) | (imm11 << 11) | (imm10_1 << 1);
294                // Sign extend
295                let imm = (imm << 11) >> 11;
296                Some(Self::Jal { rd, imm })
297            }
298            // Fence (I-type like, simplified for EM)
299            0b0001111 => {
300                if funct3 == 0b000 && rd_bits == 0 && rs1_bits == 0 {
301                    // fm is bits 31:28 — must be 0 per spec
302                    if (instruction >> 28) & 0b1111 == 0 {
303                        let pred = ((instruction >> 24) & 0xf) as u8;
304                        let succ = ((instruction >> 20) & 0xf) as u8;
305                        Some(Self::Fence { pred, succ })
306                    } else {
307                        None
308                    }
309                } else {
310                    None
311                }
312            }
313            // System instructions
314            0b1110011 => {
315                let imm = (instruction >> 20) & 0xfff;
316                if funct3 == 0 && rd_bits == 0 && rs1_bits == 0 {
317                    match imm {
318                        0 => Some(Self::Ecall),
319                        1 => Some(Self::Ebreak),
320                        _ => None,
321                    }
322                } else if funct3 == 0b001 && rd_bits == 0 && rs1_bits == 0 && imm == 0xc00 {
323                    // `0xc0001073` is emitted as `unimp`/illegal instruction by various compilers,
324                    // including Rust when it hits a panic
325                    Some(Self::Unimp)
326                } else {
327                    None
328                }
329            }
330            _ => None,
331        }
332    }
333
334    #[inline(always)]
335    fn alignment() -> u8 {
336        size_of::<u32>() as u8
337    }
338
339    #[inline(always)]
340    fn size(&self) -> u8 {
341        size_of::<u32>() as u8
342    }
343}
344
345impl<Reg> fmt::Display for Rv64Instruction<Reg>
346where
347    Reg: fmt::Display,
348{
349    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
350        match self {
351            Self::Add { rd, rs1, rs2 } => write!(f, "add {}, {}, {}", rd, rs1, rs2),
352            Self::Sub { rd, rs1, rs2 } => write!(f, "sub {}, {}, {}", rd, rs1, rs2),
353            Self::Sll { rd, rs1, rs2 } => write!(f, "sll {}, {}, {}", rd, rs1, rs2),
354            Self::Slt { rd, rs1, rs2 } => write!(f, "slt {}, {}, {}", rd, rs1, rs2),
355            Self::Sltu { rd, rs1, rs2 } => write!(f, "sltu {}, {}, {}", rd, rs1, rs2),
356            Self::Xor { rd, rs1, rs2 } => write!(f, "xor {}, {}, {}", rd, rs1, rs2),
357            Self::Srl { rd, rs1, rs2 } => write!(f, "srl {}, {}, {}", rd, rs1, rs2),
358            Self::Sra { rd, rs1, rs2 } => write!(f, "sra {}, {}, {}", rd, rs1, rs2),
359            Self::Or { rd, rs1, rs2 } => write!(f, "or {}, {}, {}", rd, rs1, rs2),
360            Self::And { rd, rs1, rs2 } => write!(f, "and {}, {}, {}", rd, rs1, rs2),
361
362            Self::Addw { rd, rs1, rs2 } => write!(f, "addw {}, {}, {}", rd, rs1, rs2),
363            Self::Subw { rd, rs1, rs2 } => write!(f, "subw {}, {}, {}", rd, rs1, rs2),
364            Self::Sllw { rd, rs1, rs2 } => write!(f, "sllw {}, {}, {}", rd, rs1, rs2),
365            Self::Srlw { rd, rs1, rs2 } => write!(f, "srlw {}, {}, {}", rd, rs1, rs2),
366            Self::Sraw { rd, rs1, rs2 } => write!(f, "sraw {}, {}, {}", rd, rs1, rs2),
367
368            Self::Addi { rd, rs1, imm } => write!(f, "addi {}, {}, {}", rd, rs1, imm),
369            Self::Slti { rd, rs1, imm } => write!(f, "slti {}, {}, {}", rd, rs1, imm),
370            Self::Sltiu { rd, rs1, imm } => write!(f, "sltiu {}, {}, {}", rd, rs1, imm),
371            Self::Xori { rd, rs1, imm } => write!(f, "xori {}, {}, {}", rd, rs1, imm),
372            Self::Ori { rd, rs1, imm } => write!(f, "ori {}, {}, {}", rd, rs1, imm),
373            Self::Andi { rd, rs1, imm } => write!(f, "andi {}, {}, {}", rd, rs1, imm),
374            Self::Slli { rd, rs1, shamt } => write!(f, "slli {}, {}, {}", rd, rs1, shamt),
375            Self::Srli { rd, rs1, shamt } => write!(f, "srli {}, {}, {}", rd, rs1, shamt),
376            Self::Srai { rd, rs1, shamt } => write!(f, "srai {}, {}, {}", rd, rs1, shamt),
377
378            Self::Addiw { rd, rs1, imm } => write!(f, "addiw {}, {}, {}", rd, rs1, imm),
379            Self::Slliw { rd, rs1, shamt } => write!(f, "slliw {}, {}, {}", rd, rs1, shamt),
380            Self::Srliw { rd, rs1, shamt } => write!(f, "srliw {}, {}, {}", rd, rs1, shamt),
381            Self::Sraiw { rd, rs1, shamt } => write!(f, "sraiw {}, {}, {}", rd, rs1, shamt),
382
383            Self::Lb { rd, rs1, imm } => write!(f, "lb {}, {}({})", rd, imm, rs1),
384            Self::Lh { rd, rs1, imm } => write!(f, "lh {}, {}({})", rd, imm, rs1),
385            Self::Lw { rd, rs1, imm } => write!(f, "lw {}, {}({})", rd, imm, rs1),
386            Self::Ld { rd, rs1, imm } => write!(f, "ld {}, {}({})", rd, imm, rs1),
387            Self::Lbu { rd, rs1, imm } => write!(f, "lbu {}, {}({})", rd, imm, rs1),
388            Self::Lhu { rd, rs1, imm } => write!(f, "lhu {}, {}({})", rd, imm, rs1),
389            Self::Lwu { rd, rs1, imm } => write!(f, "lwu {}, {}({})", rd, imm, rs1),
390
391            Self::Jalr { rd, rs1, imm } => write!(f, "jalr {}, {}({})", rd, imm, rs1),
392
393            Self::Sb { rs2, rs1, imm } => write!(f, "sb {}, {}({})", rs2, imm, rs1),
394            Self::Sh { rs2, rs1, imm } => write!(f, "sh {}, {}({})", rs2, imm, rs1),
395            Self::Sw { rs2, rs1, imm } => write!(f, "sw {}, {}({})", rs2, imm, rs1),
396            Self::Sd { rs2, rs1, imm } => write!(f, "sd {}, {}({})", rs2, imm, rs1),
397
398            Self::Beq { rs1, rs2, imm } => write!(f, "beq {}, {}, {}", rs1, rs2, imm),
399            Self::Bne { rs1, rs2, imm } => write!(f, "bne {}, {}, {}", rs1, rs2, imm),
400            Self::Blt { rs1, rs2, imm } => write!(f, "blt {}, {}, {}", rs1, rs2, imm),
401            Self::Bge { rs1, rs2, imm } => write!(f, "bge {}, {}, {}", rs1, rs2, imm),
402            Self::Bltu { rs1, rs2, imm } => write!(f, "bltu {}, {}, {}", rs1, rs2, imm),
403            Self::Bgeu { rs1, rs2, imm } => write!(f, "bgeu {}, {}, {}", rs1, rs2, imm),
404
405            Self::Lui { rd, imm } => write!(f, "lui {}, 0x{:x}", rd, imm >> 12),
406
407            Self::Auipc { rd, imm } => write!(f, "auipc {}, 0x{:x}", rd, imm >> 12),
408
409            Self::Jal { rd, imm } => write!(f, "jal {}, {}", rd, imm),
410
411            Self::Fence { pred, succ } => write!(f, "fence {}, {}", pred, succ),
412
413            Self::Ecall => write!(f, "ecall"),
414            Self::Ebreak => write!(f, "ebreak"),
415
416            Self::Unimp => write!(f, "unimp"),
417        }
418    }
419}
ab_riscv_primitives/instructions/rv64.rs

ab_riscv_primitives/instructions/
rv64.rs
