ab_riscv_primitives/instructions/rv32/zk/zkn/
zknh.rs

1//! RV32 Zknh extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::hart::HartConfig;
7use crate::instructions::{ImplementedExtension, Instruction, IsaExtension};
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12/// RISC-V RV32 Zknh instruction (SHA-256 and SHA-512 sigma/sum functions).
13///
14/// SHA-256 instructions take a single source register.
15/// SHA-512 instructions take two source registers because 64-bit operands must be split across two
16/// 32-bit registers on RV32. The register conventions differ by instruction and follow the RISC-V
17/// scalar crypto Sail model exactly:
18///
19/// - `sha512sig0l`, `sha512sig1l`: rs1 = LOW word, rs2 = HIGH word
20/// - `sha512sig0h`, `sha512sig1h`: rs1 = HIGH word, rs2 = LOW word
21/// - `sha512sum0r`, `sha512sum1r`: rs1 = LOW word, rs2 = HIGH word
22///
23/// For `sha512sum0r` and `sha512sum1r` the Sail pseudocode builds the 64-bit operand as
24/// `x[63:32] = X(rs2), x[31:0] = X(rs1)` (rs2 is the HIGH half) and writes the low 32 bits of the
25/// result to `rd`.
26#[instruction]
27#[derive(Debug, Clone, Copy)]
28#[derive_const(PartialEq, Eq)]
29#[rustfmt::skip]
30pub enum Rv32ZknhInstruction<Hart>
31where
32    Hart: HartConfig,
33{
34    // SHA-256 (single-register, identical encoding to RV64)
35    Sha256Sig0 { rd: Hart::Reg, rs1: Hart::Reg },
36    Sha256Sig1 { rd: Hart::Reg, rs1: Hart::Reg },
37    Sha256Sum0 { rd: Hart::Reg, rs1: Hart::Reg },
38    Sha256Sum1 { rd: Hart::Reg, rs1: Hart::Reg },
39    // SHA-512 (two-register, RV32-only R-type)
40    Sha512Sig0h { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
41    Sha512Sig0l { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
42    Sha512Sig1h { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
43    Sha512Sig1l { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
44    Sha512Sum0r { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
45    Sha512Sum1r { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
46}
47
48#[instruction]
49const impl<Reg, Hart> Instruction for Rv32ZknhInstruction<Hart>
50where
51    Reg: [const] Register<Type = u32>,
52    Hart: [const] HartConfig<Reg = Reg>,
53{
54    const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = &[IsaExtension::new("zknh", 1, 0)];
55
56    const ALIGNMENT: u8 = align_of::<u32>() as u8;
57
58    type Hart = Hart;
59
60    #[inline(always)]
61    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
62    fn try_decode(instruction: u32) -> Option<Self> {
63        let opcode = (instruction & 0b111_1111) as u8;
64        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
65        let funct3 = ((instruction >> 12) & 0b111) as u8;
66        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
67        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
68        // Same field as rs2 for I-type
69        let funct5 = ((instruction >> 20) & 0x1f) as u8;
70        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
71
72        match opcode {
73            // SHA-256: I-type format (OP-IMM)
74            0b001_0011 => {
75                if funct3 != 0b001 || funct7 != 0b000_1000 {
76                    None
77                } else {
78                    let rd = Reg::from_bits(rd_bits)?;
79                    let rs1 = Reg::from_bits(rs1_bits)?;
80                    match funct5 {
81                        0b0_0010 => Some(Self::Sha256Sig0 { rd, rs1 }),
82                        0b0_0011 => Some(Self::Sha256Sig1 { rd, rs1 }),
83                        0b0_0000 => Some(Self::Sha256Sum0 { rd, rs1 }),
84                        0b0_0001 => Some(Self::Sha256Sum1 { rd, rs1 }),
85                        _ => None,
86                    }
87                }
88            }
89            // SHA-512: R-type format (OP)
90            // RV32-only two-register instructions.
91            0b011_0011 => {
92                if funct3 == 0b000 {
93                    let rd = Reg::from_bits(rd_bits)?;
94                    let rs1 = Reg::from_bits(rs1_bits)?;
95                    let rs2 = Reg::from_bits(rs2_bits)?;
96                    match funct7 {
97                        // 0b010_1000 = 40
98                        0b010_1000 => Some(Self::Sha512Sum0r { rd, rs1, rs2 }),
99                        // 0b010_1001 = 41
100                        0b010_1001 => Some(Self::Sha512Sum1r { rd, rs1, rs2 }),
101                        // 0b010_1010 = 42
102                        0b010_1010 => Some(Self::Sha512Sig0l { rd, rs1, rs2 }),
103                        // 0b010_1011 = 43
104                        0b010_1011 => Some(Self::Sha512Sig1l { rd, rs1, rs2 }),
105                        // 0b010_1110 = 46
106                        0b010_1110 => Some(Self::Sha512Sig0h { rd, rs1, rs2 }),
107                        // 0b010_1111 = 47
108                        0b010_1111 => Some(Self::Sha512Sig1h { rd, rs1, rs2 }),
109                        _ => None,
110                    }
111                } else {
112                    None
113                }
114            }
115            _ => None,
116        }
117    }
118
119    #[inline(always)]
120    fn size(&self) -> u8 {
121        size_of::<u32>() as u8
122    }
123}
124
125#[instruction]
126impl<Reg, Hart> fmt::Display for Rv32ZknhInstruction<Hart>
127where
128    Reg: fmt::Display,
129    Hart: HartConfig<Reg = Reg>,
130{
131    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
132        match self {
133            Self::Sha256Sig0 { rd, rs1 } => write!(f, "sha256sig0 {rd}, {rs1}"),
134            Self::Sha256Sig1 { rd, rs1 } => write!(f, "sha256sig1 {rd}, {rs1}"),
135            Self::Sha256Sum0 { rd, rs1 } => write!(f, "sha256sum0 {rd}, {rs1}"),
136            Self::Sha256Sum1 { rd, rs1 } => write!(f, "sha256sum1 {rd}, {rs1}"),
137            Self::Sha512Sig0h { rd, rs1, rs2 } => write!(f, "sha512sig0h {rd}, {rs1}, {rs2}"),
138            Self::Sha512Sig0l { rd, rs1, rs2 } => write!(f, "sha512sig0l {rd}, {rs1}, {rs2}"),
139            Self::Sha512Sig1h { rd, rs1, rs2 } => write!(f, "sha512sig1h {rd}, {rs1}, {rs2}"),
140            Self::Sha512Sig1l { rd, rs1, rs2 } => write!(f, "sha512sig1l {rd}, {rs1}, {rs2}"),
141            Self::Sha512Sum0r { rd, rs1, rs2 } => write!(f, "sha512sum0r {rd}, {rs1}, {rs2}"),
142            Self::Sha512Sum1r { rd, rs1, rs2 } => write!(f, "sha512sum1r {rd}, {rs1}, {rs2}"),
143        }
144    }
145}
ab_riscv_primitives/instructions/rv32/zk/zkn/zknh.rs

ab_riscv_primitives/instructions/rv32/zk/zkn/
zknh.rs
